System On Chip (SOC) ASIC chipset for Smart Actuators in Distributed Propulsion Systems

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000040-000045
Author(s):  
Bhal Tulpule ◽  
Alireza R. Behbahani
Keyword(s):  
High Temperature ◽  
Embedded Systems ◽  
Risk Reduction ◽  
Control Systems ◽  
Real Time ◽  
System On Chip ◽  
Silicon On Insulator ◽  
Design Development ◽  
Sensors And Actuators ◽  
On Chip

Abstract This paper describes the results of the risk reduction testing task recently completed by Embedded Systems LLC under the Air Force SBIR contract {5} titled “Improved Full Authority Digital Engine Control (FADEC) System”. The objective of this program has been to develop a hierarchical, distributed architecture for future propulsion FADEC and aerospace control systems with flexible, scalable and reconfigurable Smart Nodes (SN) built with high temperature capable devices. A key part of this program is the design, development and validation of the System On Chip (SOC) chipset in high temperature (225 Deg. C) SOI (Silicon On Insulator) technology ASIC (Application Specific Integrated Circuit) devices. The SOC chipset designed by Embedded Systems LLC provides the scalability and reconfigurability that enables the Smart Node to interfaces with most sensors and actuators found in FADEC and other aircraft control systems. The analog portion of this 2-chip SOC chipset fabricated by Honeywell using their SOI process is working properly. The digital portion of the SOC chipset, currently implemented in a commercial temperature FPGA (Field Programmable Gate Array), contains important computational functions needed for reconfiguring the SOC and performing complex control functions, such as real time control of an actuator, The risk reduction task was therefore focused on verification and validation of these key functions in a real environment before converting the design into an ASIC. The recent successful demonstration of the real time actuator control capability has minimized the risks and cleared the way for the digital ASIC implementation. The complete high temperature SOC chipset is expected to be available in late 2016.

A System On Chip (SOC) ASIC chipset for Aerospace and Energy Exploration Applications

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000278-000284 ◽  
Author(s):  
Bhal Tulpule ◽  
Bruce Ohme ◽  
Mark Larson ◽  
Al Behbahani ◽  
John Gerety ◽  
...  
Keyword(s):  
Control System ◽  
High Temperature ◽  
Building Block ◽  
Complex Function ◽  
Wind Farms ◽  
Power Source ◽  
System On Chip ◽  
Hole Drilling ◽  
Sensors And Actuators ◽  
On Chip

This paper describes the design, key features and applications of a System On Chip (SOC) ASIC (Application Specific Integrated Circuit) chipset which was developed by Embedded Systems LLC as a part of the Smart Node based distributed control system architecture under an Air Force SBIR (Small Business Innovative Research) program {4}. The analog part of the SOC chipset has been implemented by Honeywell International under a subcontract using their high temperature SOI (Silicon On Insulator) Process. The complete chipset is expected to be available in early 2015. The key feature of the SOC chipset is that it is a reconfigurable and scalable building block that can be used to interface with most typical aerospace control system sensors and actuators. The SOC chipset captures all of the necessary functions required to power and interface with sensors such as RTD (Resistance Temperature Detectors), Strain Gauges (SG), Thermo Couples (TC) and transducers for measuring mass flow, speed, position or angle. The SOC chipset also contains all of the pre- and post-processing functions to convert electrical signals into digital words and send them on a data bus under the control of a host microprocessor. Finally, the SOC chipset contains PWM (Pulse Width Modulation) circuitry required to interface with external drives for actuators, motors, shutoff Valves etc. The SOC chipset can be powered from a Mil-Std-704F compliant power source or a conditioned DC power source. The chipset can be combined with other devices, such as memory, processor and A to D Converter to implement a high temperature capable Smart Node for localized management of sensors and actuators as a part of a distributed architecture or used as a scalable building block in a more complex function such as a FADEC (Full Authority Digital Engine Control). It is believed that the versatility of the SOC chipset makes it a well suited, affordable, scalable building block for not only aerospace controls but also for diverse applications such as down-hole drilling, energy exploration, wind farms etc. where high temperature electronics and /or high level of miniaturization is required.

scholarly journals On-Device Deep Learning Inference for System-on-Chip (SoC) Architectures

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 689
Author(s):  
Tom Springer ◽  
Elia Eiroa-Lledo ◽  
Elizabeth Stevens ◽  
Erik Linstead
Keyword(s):  
Machine Learning ◽  
Deep Learning ◽  
Real Time ◽  
Operating Systems ◽  
System On Chip ◽  
Low Latency ◽  
Management Framework ◽  
On Chip ◽  
Specialized Hardware ◽  
Deterministic Behavior

As machine learning becomes ubiquitous, the need to deploy models on real-time, embedded systems will become increasingly critical. This is especially true for deep learning solutions, whose large models pose interesting challenges for target architectures at the “edge” that are resource-constrained. The realization of machine learning, and deep learning, is being driven by the availability of specialized hardware, such as system-on-chip solutions, which provide some alleviation of constraints. Equally important, however, are the operating systems that run on this hardware, and specifically the ability to leverage commercial real-time operating systems which, unlike general purpose operating systems such as Linux, can provide the low-latency, deterministic execution required for embedded, and potentially safety-critical, applications at the edge. Despite this, studies considering the integration of real-time operating systems, specialized hardware, and machine learning/deep learning algorithms remain limited. In particular, better mechanisms for real-time scheduling in the context of machine learning applications will prove to be critical as these technologies move to the edge. In order to address some of these challenges, we present a resource management framework designed to provide a dynamic on-device approach to the allocation and scheduling of limited resources in a real-time processing environment. These types of mechanisms are necessary to support the deterministic behavior required by the control components contained in the edge nodes. To validate the effectiveness of our approach, we applied rigorous schedulability analysis to a large set of randomly generated simulated task sets and then verified the most time critical applications, such as the control tasks which maintained low-latency deterministic behavior even during off-nominal conditions. The practicality of our scheduling framework was demonstrated by integrating it into a commercial real-time operating system (VxWorks) then running a typical deep learning image processing application to perform simple object detection. The results indicate that our proposed resource management framework can be leveraged to facilitate integration of machine learning algorithms with real-time operating systems and embedded platforms, including widely-used, industry-standard real-time operating systems.

Microsense

2016 ◽  
Vol 7 (3) ◽  
pp. 38-55
Author(s):  
Srinivasa K.G. ◽  
Ganesh Hegde ◽  
Kushagra Mishra ◽  
Mohammad Nabeel Siddiqui ◽  
Abhishek Kumar ◽  
...  
Keyword(s):  
Real Time ◽  
Nodal Point ◽  
System On Chip ◽  
Streaming Data ◽  
Portable Devices ◽  
Time Data ◽  
Unified Framework ◽  
Real Time Data ◽  
Varied Degree ◽  
On Chip

With the advancement of portable devices and sensors, there has been a need to build a universal framework, which can serve as a nodal point to aggregate data from different kinds of devices and sensors. We propose a unified framework that will provide a robust set of guidelines for sensors with varied degree of complexities connected to common set of System-on-Chip (SoC). These will help to monitor, control and visualize real time data coming from different type of sensors connected to these SoCs. We have defined a set of APIs, which will help the sensors to register with the server. These APIs will be the standard to which the sensors will comply while streaming data when connected to the client platforms.

scholarly journals An Autonomous Path Controller in a System on Chip for Shrimp Robot

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 441 ◽  
Author(s):  
Sergio Barrios-dV ◽  
Michel Lopez-Franco ◽  
Jorge D. Rios ◽  
Nancy Arana-Daniel ◽  
Carlos Lopez-Franco ◽  
...  
Keyword(s):  
Path Planning ◽  
Real Time ◽  
Trajectory Tracking ◽  
Neural Control ◽  
Tracking System ◽  
Kinematic Model ◽  
System On Chip ◽  
Optimal Controller ◽  
Real Time System ◽  
On Chip

This paper presents a path planning and trajectory tracking system for a BlueBotics Shrimp III®, which is an articulate mobile robot for rough terrain navigation. The system includes a decentralized neural inverse optimal controller, an inverse kinematic model, and a path-planning algorithm. The motor control is obtained based on a discrete-time recurrent high order neural network trained with an extended Kalman filter, and an inverse optimal controller designed without solving the Hamilton Jacobi Bellman equation. To operate the whole system in a real-time application, a Xilinx Zynq® System on Chip (SoC) is used. This implementation allows for a good performance and fast calculations in real-time, in a way that the robot can explore and navigate autonomously in unstructured environments. Therefore, this paper presents the design and implementation of a real-time system for robot navigation that integrates, in a Xilinx Zynq® System on Chip, algorithms of neural control, image processing, path planning, and inverse kinematics and trajectory tracking.

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