Non-Conductive Film (NCF) with No Voiding and High Reliability

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 1-28 ◽  
Author(s):  
Edgardo Anzures ◽  
Anupam Choubey ◽  
Avin Dhoble ◽  
David Fleming ◽  
Robert Barr ◽  
...  
Keyword(s):  
High Reliability ◽  
New Technology ◽  
High Volume ◽  
Temperature Cycling ◽  
Significant Activity ◽  
Wafer Level ◽  
Dimensional Changes ◽  
Conductive Film ◽  
Thermocompression Bonding ◽  
Multiple Devices

There has been significant activity in recent years to develop Non-Conductive Films (NCF), which are also known as Pre-Applied Underfills (PAUF) and Wafer Level Underfills (WLUF), for use in the High Volume Manufacturing (HVM) of 2.5D and 3D packages. They are essentially underfills in laminate film form. Like other underfills, they ensure the integrity of the electrical interconnects in a package by mitigating stress, acting as an adhesive to bind the package together, and encapsulating to protect against moisture and other unwanted materials that can compromise electrical connectivity. NCF's are seen as an alternative to the more traditional capillary underfills, especially in devices with finer pitch, smaller gap, and larger size. Since the NCF can be applied to multiple devices simultaneously, this new technology has an advantage over capillary underfills in HVM. These film-type underfills can be applied to wafers (PAUF, WLUF, NCF) or substrates (PAUF, NCF). Two key attributes of any underfill are no voiding and high reliability. No voiding is an essential requirement for high reliability. Voiding in NCF materials can result from the lamination and thermocompression bonding (TCB) processes. Voiding under the die can manifest from a variety of causes, including some of the following: (1) volatilization of materials in the coating, (2) dimensional changes within the coating during processing, (3) poor fundamental conformation to surface topography during film lamination and (4) ineffective air release during TCB due to un-optimized material flow. Unwanted issues such as reduced adhesion, solder shorting, increased moisture uptake and reduced stress mitigation can result from the presence of voids in the NCF. Pressure cure after joining is one method for eliminating voids in NCF materials. An earlier version of the NCF discussed in this study required pressure to eliminate voids after TCB. Pressure curing, however, adds process steps and is not accepted by all manufacturers. An improved NCF formulation and bonding process has resulted in a void-free NCF that does not require pressure cure for void elimination. This improved version not only addresses voiding after bonding, but also it has been proven to be very reliable in the presence of extreme temperatures, high humidity and temperature cycling. No one test is sufficient to adequately determine the long term reliability of NCF materials so a battery of tests was run to conduct a comprehensive assessment. The reliability evaluation results demonstrate that this newly developed NCF exhibits not only no voiding after TCB without the need for pressure cure, but also high reliability to various forms of temperature and humidity stress testing.

Assembly Equipment Requirements for Next Generation Advanced Packaging

2016 ◽  
Vol 2016 (1) ◽  
pp. 000321-000325
Author(s):  
Bob Chylak ◽  
Horst Clauberg ◽  
Tom Strothmann
Keyword(s):  
Capital Investment ◽  
Flip Chip ◽  
High Volume ◽  
Electrical Performance ◽  
Wafer Level ◽  
Considerable Uncertainty ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
The Impact ◽  
3D Package

Abstract Device packaging is undergoing a proliferation of assembly options within the ever-expanding category of Advanced Packaging. Fan Out-Wafer Level Packages are achieving wide adoption based on improved performance and reduced package size and new System in Package products are coming to market in FOWLP, 2.5D and 3D package formats with the full capability to leverage heterogeneous integration in small package profiles. While the wide-spread adoption of thermocompression bonding and 2.5D packages predicted several years ago has not materialized to the extent predicted, advanced memory modules assembled by TCB are in high volume manufacturing, as are some high-end GPUs with integrated memory on Si interposer. High accuracy flip chip has been pushed to fine pitches that were difficult to imagine only three years ago and innovation in substrates and bonder technology is pushing the throughput and pitch capability even further. The packaging landscape, once dominated by a few large assembly providers, now includes turn-key packaging initiatives from the foundries with an expanding set of fan-out packing options. The fan-out processes include face-up and face-down methods, die first and die last methods and 2.5D or 3D package options. Selection of the most appropriate packaging technology from the combined aspects of electrical performance, form-factor, yield and cost presents a complex problem with considerable uncertainty and high risk for capital investment. To address this problem, the industry demands flexible manufacturing solutions that can be modified and upgraded to accommodate a changing assembly environment. This presentation will present the assembly process flows for various packaging options and discuss the key aspects of the process that influence throughput, accuracy and other key quality metrics, such as package warpage. These process flows in turn impose design constraints on submodules of the bonder. It will be shown that thoughtfully designed machine architecture allows for interchangeable and upgradeable submodules that can support nearly the entire range of assembly options. As an example, a nimble, low weight, medium force, constant heat bondhead for high throughput FOWLP can be interchanged with a high force, pulse heater bondhead to support low stress/low warpage thermocompression bonding. The various configuration options for a flexible advanced packaging bonder will be reviewed along with the impact of configuration changes on throughput and accuracy.

Intermittent Failures in High Pin Count Packaging

2006 ◽  
Author(s):  
Ramesh Varma ◽  
Richard Brooks ◽  
Ronald Twist ◽  
James Arnold ◽  
Cleston Messick
Keyword(s):  
Failure Analysis ◽  
Shape Analysis ◽  
State Of The Art ◽  
Process Variation ◽  
High Reliability ◽  
Temperature Cycling ◽  
Assembly Process ◽  
System Failures ◽  
Industrial Grade ◽  
Corrective Actions

Abstract In a prequalification effort to evaluate the assembly process for the industrial grade high pin count devices for use in a high reliability application, one device exhibited characteristics that, without corrective actions and/or extensive screening, may lead to intermittent system failures and unacceptable reliability. Five methodologies confirmed this conclusion: (1) low post-decapsulation wire pull results; (2) bond shape analysis showed process variation; (3) Failure Analysis (FA) using state of the art equipment determined the root causes and verified the low wire pull results; (4) temperature cycling parts while monitoring, showed intermittent failures, and (5) parts tested from other vendors using the same techniques passed all limits.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Ultra-High-Density Interconnect Enabled by Hybrid Bonding for Heterogeneous Integration: Interfacial Characteristics

2021 ◽  
Author(s):  
Mei-Chien Lu
Keyword(s):  
Performance Metrics ◽  
High Volume ◽  
Image Sensor ◽  
Structure Design ◽  
High Density ◽  
Heterogeneous Integration ◽  
Wafer Level ◽  
Bonding Area ◽  
The Impact ◽  
Interfacial Characteristics

Abstract Hybrid bonding has been explored for more than a decade and implemented recently in high volume production at wafer-to-wafer level for image sensor applications to enable high performance chip-stacking architectures with ultra-high-density chip-to-chip interconnect. The feasibility of sub-micron hybrid bond pitch leading to ultra-high-density chip-to-chip interconnect has been demonstrated due to the elimination of solder bridging issues from microbump method. Hybrid bonding has also been actively considered for logic and memory chip-stacking, chiplets, and heterogeneous integration in general but encountering additional challenges for bonding at die-to-wafer or die-to-die level. Overlay precision, throughput, wafer dicing are among the main causes. Widening the process margin against overlay error by designing innovative hybrid bonding pad structure is highly desirable. This work proposes a method to evaluate these hybrid bonding pad structure designs and to assess the potential performance metrics by analyzing interfacial characteristics at design phase. The bonding areas and ratios of copper-copper, copper-dielectric, and dielectric-dielectric are the proposed key parameters. The correlation between bonding area ratios and overlay errors can provide insights on the sensitivity to process margins. Nonetheless, the impact of copper recess or protrusion associated with bonding area ratios are also highlighted. The proposed method is demonstrated by examining and analyzing the hybrid bonding pad structure design concepts from a few cases reported in literatures as examples. Concerns are identified for elaboration in future designs and optimizations.

Cloud Computing for Secure Services in E-Government Architecture

2016 ◽  
pp. 1727-1746
Author(s):  
Sajjad Hashemi ◽  
Khalil Monfaredi ◽  
Seyyed Yasser Hashemi
Keyword(s):  
Cloud Computing ◽  
Query Processing ◽  
Data Security ◽  
New Technology ◽  
High Volume ◽  
Maximum Efficiency ◽  
Government Services ◽  
Security Service ◽  
Data Center Management ◽  
The Face

E-government tries to take advantage of new technology to provide better service to citizens. Some of the main challenges in the face of E-government are query processing high volume applications, data center management, data security and E-government services. Cloud computing can be a good option for responding to these issues and fixing them, and guarantee the realization of E-government, with maximum efficiency and maximum safety. In this paper, the authors propose a novel architecture for E-government by using Cloud computing architecture which can largely increase the integrity and security service in E-government, and also increase users' confidence in the system and may lead to increased participation.

Flip-Chip Flux Evolution

2019 ◽  
Vol 2019 (1) ◽  
pp. 000115-000119 ◽  
Author(s):  
Andy Mackie ◽  
Hyoryoon Jo ◽  
Sze Pei Lim
Keyword(s):  
Flip Chip ◽  
Elevated Temperatures ◽  
High Volume ◽  
Automotive Electronics ◽  
Assembly Process ◽  
Surface Finishes ◽  
Solder Bumps ◽  
Thermocompression Bonding ◽  
Advanced Packaging ◽  
Flip Chip Assembly

Abstract Flip-chip assembly accounts for more than 80% of the advanced packaging technology platform, compared to fan-in, fan-out, embedded die, and through silicon via (TSV). Flip-chip interconnect remains a critical assembly process for large die used in artificial intelligence processors; thin die that warps at elevated temperatures; heterogeneous integration in SiP applications; flip-chip on leadframe; and MicroLED die usage. This paper will first outline trends in evolving flip-chip and direct chip placement (DCP) technology, then will examine the changing nature of the solder bump, the interconnect itself, and the substrate. Many variables of the flip-chip assembly process will be discussed, including standard solder bumps to micro Cu-pillar bumps with different alloys; different pad surface finishes of Cu OSP, NiAu, and solder on pad (SOP); and from regular pads on substrates to bond-on-trace applications. A major focus will be on flip-chip assembly methods, from old C4 conventional reflow processing to thermocompression bonding (TCB), and the latest laser assisted bonding (LAB) technology, with an emphasis on how the usage of different technologies necessitates different assembly materials, especially fluxes. Flip-chip fluxes such as the commonly used water-washable flux, the standard no-clean flux, and the ultra-low residue flux, and how these fluxes react to different processing methods, will be an area of discussion. Finally, the paper will examine the need for increased reliability as the technology inevitably moves into the high-volume, zero-defect arena of automotive electronics.

Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 000545-000566
Author(s):  
John Hunt ◽  
Adren Hsieh ◽  
Eddie Tsai ◽  
Chienfan Chen ◽  
Tsaiying Wang
Keyword(s):  
Temperature Cycling ◽  
Wafer Level ◽  
Development Activity ◽  
Wafer Level Packaging ◽  
First Case ◽  
Mask Design ◽  
To Come ◽  
And Performance ◽  
Reliability Performance ◽  
The Impact

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity. With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die. For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured. We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.

Embedded Die Packages and Modules for Power Electronics Applications

2016 ◽  
Vol 2016 (DPC) ◽  
pp. 001918-001947 ◽  
Author(s):  
Lars Boettcher ◽  
S. Karaszkiewicz ◽  
D. Manessis ◽  
A. Ostmann
Keyword(s):  
Power Electronics ◽  
Power Efficiency ◽  
High Reliability ◽  
Heat Removal ◽  
Testing Temperature ◽  
Temperature Cycling ◽  
Switching Frequency ◽  
Large Area ◽  
Power Modules ◽  
Embedded Power

Packages and modules with embedded semiconductor dies are of interest for various application fields and power classes. First packages in the lower power range are available in volume production since almost six years. Recent developments focus on medium and higher power applications raging over 500W into the kW range. Different approaches are available to realize such packages and modules. This paper will give an overview and detailed description of the latest approaches for such embedded die structures. In common of all of these approaches, is the use of laminate based die embedding, which uses standard PCB manufacturing technologies. Main differences are the used base substrate, which can still be a ceramic (DBC), Cu leadframe or high current substrate. Examples for the different methods will be given. As the main part, this paper will describe concepts, which enable significant smaller form-factor of power electronics modules, thereby allowing for lower price, high reliability, capability of direct mounting on e.g. a motor so as to form one unit with the motor housing, wide switching frequency range (for large application field) and high power efficiency. The innovative character of this packaging concept is the idea to embed the power drive components (IGBTs, MOSFETs, diode) as thinned chips into epoxy-resin layer built-up and to realize large-area interconnections on both sides by direct copper plating the dies to form a conductor structure with lowest possible electrical impedance and to achieve an optimum heat removal. In this way a thin core is formed on a large panel format which is called Embedded Power Core. The paper will specifically highlight the first results on manufacturing an embedded power discrete package as an example of an embedded power core containing a thin rectifier diode. For module realization, the power cores are interconnected to insulated metal substrates (IMS) by the use of Ag sintering interconnection technologies for the final manufacturing of Power modules. The paper will elaborate on the sintering process for Power Core/IMS interconnections, the microscopically features of the sintered interfaces, and the lateral filling of the sintering gap with epoxy prepregs. Firstly, 500W power modules were manufactured using this approach. Reliability testing results, solder reflow testing, temperature cycling test and active power cycling, will be discussed in detail.

Automated Metrology Improves Productivity and Yields for Wafer Level Packaging in High Volume Manufacturing

2014 ◽  
Vol 2014 (1) ◽  
pp. 000155-000160
Author(s):  
Jin You Zao ◽  
Bong Yin Yen ◽  
Lim Beng Kuan ◽  
John Thornell ◽  
Darcy Hart ◽  
...  
Keyword(s):  
Process Control ◽  
High Volume ◽  
Critical Dimension ◽  
Thickness Measurement ◽  
Electrical Performance ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Under Sampling ◽  
Line Process ◽  
Increasing Demand

Wafer Bumping In-line Process control of Wafer-Level Chip Scale Package (WLCSP) requires accurate measurement of bump features during processing. These bump features include critical dimension of Redistribution Layer (RDL), Under Bump Metal (UBM) and transparent polyimide thickness. For a 4-Mask Layer Cu plated WLCSP, accurate feature thickness measurement is required for both the Redistribution Layer (RDL) and Under Bump Metal (UBM) to ensure consistent delivery of good electrical performance and package reliability. This is especially important as WLCSP is moving towards finer feature size and pitch to meet increasing demand for smaller form factor. This paper reports the development of an automated Critical Dimension (CD) measurement solution capable of measuring features at pre-defined locations on different topology both under sampling and full inspection mode on wafer. The solution is fully scalable to meet the requirement of high product-mix HVM environment, by highly adaptive to different features on different products for which measurement needs to be automated for effective process control.

BCB-Based Dry Film low k Permanent Polymer with sub 4-μm Vias for Advanced WLP and FO-WLP Applications

2015 ◽  
Vol 2015 (1) ◽  
pp. 000079-000085 ◽  
Author(s):  
Michael Toepper ◽  
Tanja Braun ◽  
Robert Gernhardt ◽  
Martin Wilke ◽  
Piotr Mackowiak ◽  
...  
Keyword(s):  
Laser Scanning ◽  
New Technology ◽  
Side Wall ◽  
Wafer Level ◽  
Major Barrier ◽  
Wafer Level Packaging ◽  
And Performance ◽  
Low K ◽  
Metallization Process ◽  
Dry Film

There is a strong demand to increase the routing density of the RDL to match the requirements for future microelectronic systems which are mainly miniaturization and performance. Photo-resists for structuring the metallization or acting as a mold for electroplating are common for very fine lines and spaces due to the developments in the front-end processing. For example chemical amplified Photo-resists are now moving in the back-end and wafer level packaging process. The results are mainly governed by the performance of the equipment i.e. the photo-tool. This is different for the permanent dielectric polymer material. The major difference in photo-resists and dielectric photo-polymer are the different functions of the material systems. Photo-resists are only temporary masks for subsequent process steps like etching and plating. This is different for the photo-polymers which are a permanent part of the future systems. In this paper a new technology is discussed which uses a laser scanning ablation process and BCB-Based Dry Film low k Permanent Polymer. Laser ablation of polymers is in principle not a new technology. Low speed and high cost was the major barrier. But the combination of a scanning technology together with quartz masks has opened this technology to overcome the limitation of the current photo-polymer process. The new technology is described in detail and the results of structuring BCB-Based Films down to less than 4 μm via diameter in a 15 μm thick film has been shown. The via side wall can be controlled by the fluence of the laser pulse. Test structures have been designed and fabricated to demonstrate the excellent electrical resistivity of the vias using a two-layer metallization process.

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