Lithography for Wafer Level Packaging for LED Manufacturing

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001253-001276
Author(s):  
Michael Hornung
Keyword(s):  
Angular Spectrum ◽  
Optical Systems ◽  
Attractive Alternative ◽  
Market Demand ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Illumination System ◽  
Ic Manufacturing ◽  
Mask Aligner ◽  
Diffraction Effects

Since LED became an attractive alternative for general lighting, the market demand for higher brightness, higher efficiency and lower costs was the motivation for improving the LED technology. Locking in on the LED manufacturing process, most steps are on die-level after chip singularizing and therefore the costs are dominated by the huge number of dies which could often reach several thousand dies on one wafer. It's obvious that WLP has a clear benefit for LED packaging and it is also the path to success for LED manufacturing. Moreover, it also allows the implementation and integration of additional functionalities to the LED chip module, e.g. electrical connects, Zener-Diode, mirrors, optics drivers etc. Nonetheless, a clear important aspect to adopt WLP for LED manufacturing is to benefit from existing know-how of the IC manufacturing technology and of the experience of the equipment suppliers for this industry. However, the equipment needs to be optimized for the dedicated LED-WLP application. For example, microlithography with mask aligners is widely used for LED chip manufacturing, but the illumination system of these mask aligner are typically optimized for highest resolution which means contact lithography. For LED-WLP the optical systems must be capable for customized illumination for proximity lithography, where the photo mask and the wafer are separated by a proximity gap of typically 30 to 200 microns. Here, diffraction effects limit the resolution and fidelity of the pattern generated or printed in the photoresist. These diffraction effects are related to the mask pattern and the angular spectrum of the illumination light. The requirements on the lithography process for LED-WLP will be explained and discussed. Experimental results of perfect 3D patterning on topographies up to several hundred microns will be shown.

Mechanical Analyses of Advanced Multi-Chip Embedded Wafer Level Packages

2013 ◽  
Vol 740 ◽  
pp. 289-294
Author(s):  
Siow Ling Ho ◽  
Lin Bu ◽  
Dexter Velez Sorono ◽  
Ser Choong Chong ◽  
Tai Chong Chai ◽  
...  
Keyword(s):  
Cycling Performance ◽  
Market Demand ◽  
Wafer Level ◽  
Molding Process ◽  
Molding Compound ◽  
Mechanical Effects ◽  
Wafer Level Packaging ◽  
Attractive Option ◽  
Small Form Factor ◽  
Improved Accuracy

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

Atomic Resolution in Crystal Aperture Stem

1990 ◽  
Vol 48 (1) ◽  
pp. 236-237
Author(s):  
J T Fourie
Keyword(s):  
Optical System ◽  
Spherical Aberration ◽  
Three Dimensional ◽  
Transmission Function ◽  
Optical Systems ◽  
Bragg Angle ◽  
Electron Optical System ◽  
Intimate Contact ◽  
Diffraction Effects ◽  
Design Aspect

The attempts at improvement of electron optical systems to date, have largely been directed towards the design aspect of magnetic lenses and towards the establishment of ideal lens combinations. In the present work the emphasis has been placed on the utilization of a unique three-dimensional crystal objective aperture within a standard electron optical system with the aim to reduce the spherical aberration without introducing diffraction effects. A brief summary of this work together with a description of results obtained recently, will be given.The concept of utilizing a crystal as aperture in an electron optical system was introduced by Fourie who employed a {111} crystal foil as a collector aperture, by mounting the sample directly on top of the foil and in intimate contact with the foil. In the present work the sample was mounted on the bottom of the foil so that the crystal would function as an objective or probe forming aperture. The transmission function of such a crystal aperture depends on the thickness, t, and the orientation of the foil. The expression for calculating the transmission function was derived by Hashimoto, Howie and Whelan on the basis of the electron equivalent of the Borrmann anomalous absorption effect in crystals. In Fig. 1 the functions for a g220 diffraction vector and t = 0.53 and 1.0 μm are shown. Here n= Θ‒ΘB, where Θ is the angle between the incident ray and the (hkl) planes, and ΘB is the Bragg angle.

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

3D IC/Stacked Device Fault Isolation Using 3D Magnetic Field Imaging

2014 ◽  
Author(s):  
A. Orozco ◽  
N.E. Gagliolo ◽  
C. Rowlett ◽  
E. Wong ◽  
A. Moghe ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Fault Isolation ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Current Location ◽  
Geometrical Information ◽  
Magnetic Field Imaging ◽  
Silicon Vias ◽  
Non Destructive ◽  
Field Imaging

Abstract The need to increase transistor packing density beyond Moore's Law and the need for expanding functionality, realestate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques and require novel non-destructive, true 3D Failure Localization techniques. We describe in this paper innovations in Magnetic Field Imaging for FI that allow current 3D mapping and extraction of geometrical information about current location for non-destructive fault isolation at every chip level in a 3D stack.

scholarly journals Utilizing an Adaptive Grey Model for Short-Term Time Series Forecasting: A Case Study of Wafer-Level Packaging

2013 ◽  
Vol 2013 ◽  
pp. 1-6 ◽  
Author(s):  
Che-Jung Chang ◽  
Der-Chiang Li ◽  
Wen-Li Dai ◽  
Chien-Chih Chen
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing System ◽  
Grey System Theory ◽  
Grey Model ◽  
Grey System ◽  
Wafer Level ◽  
Short Term ◽  
Packaging Process ◽  
Wafer Level Packaging

The wafer-level packaging process is an important technology used in semiconductor manufacturing, and how to effectively control this manufacturing system is thus an important issue for packaging firms. One way to aid in this process is to use a forecasting tool. However, the number of observations collected in the early stages of this process is usually too few to use with traditional forecasting techniques, and thus inaccurate results are obtained. One potential solution to this problem is the use of grey system theory, with its feature of small dataset modeling. This study thus uses the AGM(1,1) grey model to solve the problem of forecasting in the pilot run stage of the packaging process. The experimental results show that the grey approach is an appropriate and effective forecasting tool for use with small datasets and that it can be applied to improve the wafer-level packaging process.

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