The Reliability Study of a High density Multi Chip Packaging with Folding Flexible Substrate

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001846-001969
Author(s):  
Yin Wen ◽  
Bo Zhang ◽  
Yuan Lu ◽  
Liao Anmou ◽  
Du Tianmin ◽  
...  
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
Flexible Substrate ◽  
Open Circuit ◽  
High Density ◽  
Core Material ◽  
Test Results ◽  
Electrical Measurements ◽  
High Frequency Signal ◽  
Significant Change

In this century, the IC packaging technology continues to make progress at astounding rate to meet the increasing requirements in many fields[1]. High density packaging is normally achieved by using various chip and/or package staking. Due to itsunique bending characteristics, flex substrate has become an ideal candidate for high density 3D packaging, especially applied for the packaging of medical products[2,3]. In this paper, we focus on the process development details of a flexible package, and investigate the main reliability problems through a series of reliability tests. There were three chips in the 3D flexible packaging structure used in our experiments. The center chip had a larger size of 5.95à —4.35mm2, while the edge ones were smaller and had the same size of 1.95à —1.95mm2. The thickness of all the three chips was the same, 200ÃŽ ¼m. All the chips had daisy chain testing structure. The ball diameter and pitch of the bumps were 250ÃŽ ¼m and 400ÃŽ ¼m, respectively. The substrate was a double-layer non-gel flexible substrate, which had polyimide as the core material (dielectric constantâ ‰ ˆ4). The substrate had a dimension of 16.9mmà —5.5mm2, and a total thickness of 80ÃŽ ¼m. Differential transmission line and DC test pads were designed in the testing circuit for high frequency signal and DC electric test. The dimension of the 3D package after folding was about 6à —6.6à —1.3mm3. The assembly process flow is as follows: All the chips were connected to a flexible substrate by using flip-chip bonding process. After underfilling was applied and cured, the two edge chips were folded and stacked onto the center chip. Then encapsulation and BGA ball dropping were followed. By flexible folding and chip stacking, the overall package size was reduced. We chose an epoxy based material as underfilling and encapsulation. X-ray check and c-scan test showed that the encapsulation had no voids in most samples. Autoclave (RH 95%, 125Ã’ °C, 96 hours) and multireflow (260â „ ƒ for 5 times) test were designed to assess the flexible structure and check the package reliability. Electrical measurements were performed to monitor and check the REL output. Some of the important electrical test results are summarized below: (1) After the multireflow test, some of the 2D unfolding samples showed open circuit in DC test, especially around the vicinity of the larger chip in the center. The DC test results of 3D samples showed no significant change after multireflow, while cross-section image showed no delamination in these area. (2) After the autoclave test, open circuit could be observed in most 2D unfolding samples near the region of the larger chip in the center, while open circuit could be seen in some smaller chip region too. For the other good parts, resistance showed an increase of 150–200% than before. The DC test results of 3D samples showed no significant change after autoclave, and the cross-section image showed no delamination in these area. (3) It could be presumed that the center region of the large chip was the weakest link of this package. 3D folding and encapsulation had reinforcement action on the flexible substrate.

Optimizing System-on-Film (SOF) Design Using Finite Element Analysis

2011 ◽  
Author(s):  
Vikram Venkatadri ◽  
Mark Downey ◽  
Xiaojie Xue ◽  
Dipak Sengupta ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Flip Chip ◽  
Flexible Substrate ◽  
High Density ◽  
Design Solution ◽  
Design Parameters ◽  
Optimized Design ◽  
Element Analysis ◽  
Bonding Parameters

System-On-Film (SOF) module is a complex integration of a fine pitch high density die and surface mounted discrete devices on a polyimide (PI) film laminate. The die is connected to the film using a thermo-compression flip-chip bonding (TCB) process which is capable of providing a very high density interconnect at less than 50um pitch. Several design and bonding parameters have to be controlled in order to achieve a reliable bond between the Au bumps on the die and the Sn plated Cu traces on the PI film. In the current work, the TCB process is studied using Finite Element Analysis (FEA) to optimize the design parameters and assure proper process margins. The resultant forces acting on the bump-to-trace interfaces are quantified across the different potential geometrical combinations. Baseline simulations showed higher stresses on specific bump locations and stress gradients acting on the bumps along the different sides of the die. These observations were correlated to both the failures and near failures on the actual test vehicles. Further simulations were then utilized to optimize and navigate design tradeoffs at both the die and flexible substrate design levels for a more robust design solution. Construction analysis performed on parts built using optimized design parameters showed significant improvements and correlated well with the simulation results.

Ultra-Thin and High-Density Packaging Using Both Sides Flip Chip Technology

2003 ◽  
Author(s):  
Kazuto Nishida ◽  
Kazumichi Shimizu ◽  
Michiro Yoshino ◽  
Hideo Koguchi ◽  
Nipon Taweejun
Keyword(s):  
Cross Section ◽  
Flip Chip ◽  
High Capacity ◽  
High Density ◽  
Thickness Direction ◽  
The Finite Element Method ◽  
Memory Card ◽  
Chip Technology ◽  
Chip Size ◽  
High Density Packaging

We have developed a high-density packaging technology by using a thin IC and a thin substrate and bonding it by new flip chip technology. Numerical analysis with the finite element method (FEM) as well experiments clearly showed that deflection of the IC and reliability were affected by the IC thickness. Consequently, reliability could be improved by reducing IC thickness. The dependency of the life in single-sided CSP and both-sided CSP on the thickness of IC and substrate could be expressed using a normal stress in the thickness direction and shear stress in the vertical cross section, respectively. Moreover, a both-sided flip chip approach solved the problem of warpage. A high-capacity memory card of 512 MB was put to practical use by applying these results. This increased the Si density by four times over that of a conventional chip-size package (CSP).

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

scholarly journals Confinement effects for rubberised concrete in tubular steel cross-sections under combined loading

2021 ◽  
Vol 21 (2) ◽  
Author(s):  
A. Mujdeci ◽  
D. V. Bompa ◽  
A. Y. Elghazouli
Keyword(s):  
Axial Compression ◽  
Cross Section ◽  
Cross Sections ◽  
Image Correlation ◽  
Combined Loading ◽  
Test Results ◽  
Compression Tests ◽  
Confinement Effects ◽  
Rubber Content ◽  
Dependent Modification

AbstractThis paper describes an experimental investigation into confinement effects provided by circular tubular sections to rubberised concrete materials under combined loading. The tests include specimens with 0%, 30% and 60% rubber replacement of mineral aggregates by volume. After describing the experimental arrangements and specimen details, the results of bending and eccentric compression tests are presented, together with complementary axial compression tests on stub-column samples. Tests on hollow steel specimens are also included for comparison purposes. Particular focus is given to assessing the confinement effects in the infill concrete as well as their influence on the axial–bending cross-section strength interaction. The results show that whilst the capacity is reduced with the increase in the rubber replacement ratio, an enhanced confinement action is obtained for high rubber content concrete compared with conventional materials. Test measurements by means of digital image correlation techniques show that the confinement in axial compression and the neutral axis position under combined loading depend on the rubber content. Analytical procedures for determining the capacity of rubberised concrete infilled cross-sections are also considered based on the test results as well as those from a collated database and then compared with available recommendations. Rubber content-dependent modification factors are proposed to provide more realistic representations of the axial and flexural cross-section capacities. The test results and observations are used, in conjunction with a number of analytical assessments, to highlight the main parameters influencing the behaviour and to propose simplified expressions for determining the cross-section strength under combined compression and bending.

scholarly journals Experimental and Numerical Investigation of the ECAP Processed Copper: Microstructural Evolution, Crystallographic Texture and Hardness Homogeneity

Metals ◽  
2021 ◽  
Vol 11 (4) ◽  
pp. 607
Author(s):  
A. I. Alateyah ◽  
Mohamed M. Z. Ahmed ◽  
Yasser Zedan ◽  
H. Abd El-Hafez ◽  
Majed O. Alawad ◽  
...  
Keyword(s):  
Grain Size ◽  
Equal Channel Angular Pressing ◽  
Cross Section ◽  
Room Temperature ◽  
Pure Copper ◽  
High Density ◽  
Ecap Processing ◽  
Heterogeneous Distribution ◽  
Angular Pressing ◽  
Average Grain Size

The current study presents a detailed investigation for the equal channel angular pressing of pure copper through two regimes. The first was equal channel angular pressing (ECAP) processing at room temperature and the second was ECAP processing at 200 °C for up to 4-passes of route Bc. The grain structure and texture was investigated using electron back scattering diffraction (EBSD) across the whole sample cross-section and also the hardness and the tensile properties. The microstructure obtained after 1-pass at room temperature revealed finer equiaxed grains of about 3.89 µm down to submicrons with a high density of twin compared to the starting material. Additionally, a notable increase in the low angle grain boundaries (LAGBs) density was observed. This microstructure was found to be homogenous through the sample cross section. Further straining up to 2-passes showed a significant reduction of the average grain size to 2.97 µm with observable heterogeneous distribution of grains size. On the other hand, increasing the strain up to 4-passes enhanced the homogeneity of grain size distribution. The texture after 4-passes resembled the simple shear texture with about 7 times random. Conducting the ECAP processing at 200 °C resulted in a severely deformed microstructure with the highest fraction of submicron grains and high density of substructures was also observed. ECAP processing through 4-passes at room temperature experienced a significant increase in both hardness and tensile strength up to 180% and 124%, respectively.

Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

2002 ◽  
Vol 124 (3) ◽  
pp. 205-211 ◽  
Author(s):  
John H. Lau ◽  
S. W. Ricky Lee ◽  
Stephen H. Pan ◽  
Chris Chang
Keyword(s):  
Cross Sections ◽  
Flip Chip ◽  
Printed Circuit Board ◽  
Low Cost ◽  
Circuit Board ◽  
Test Results ◽  
Pcb Assembly ◽  
Creep Analysis ◽  
Chip Scale Package ◽  
Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

High-Density Through-Wafer Electrical Interconnects in Pyrex Substrate Integrated With Micromirror Array

2003 ◽  
Author(s):  
C. C. Wang ◽  
T. D. Kudrle ◽  
M. Bancu ◽  
J. Hsiao ◽  
C. H. Mastrangelo
Keyword(s):  
Flip Chip ◽  
High Density ◽  
Anodic Bonding ◽  
Thermal Coefficient ◽  
Electrical Interconnects ◽  
Via Holes ◽  
Multiple Levels ◽  
Micromirror Array

A method for the construction of high density (2.4 mm−2) vertical leads through a pyrex substrate is presented. The pyrex substrate behaves as a TCE (Thermal Coefficient of Expansion) matched interposer that permits anodic bonding of silicon micromirrors on one side and flip-chip bumping of multiplexing electronic chips on its opposite side. Electrical leads consist of 250±25 μm-diameter holes formed by AJM machining and coated with evaporated Au yielding via resistances of 0.5–0.7 Ω. The via holes are sealed with a new spin-cast polyimide tenting process that enables the subsequent patterning of multiple levels of metal using conventional lithographic techniques.

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