TSV Resist and Residue Removal

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 001596-001620
Author(s):  
Laura Mauer ◽  
John Taddei ◽  
Ramey Youssef ◽  
Kimberly Pollard ◽  
Allison Rector

3D integration is the most active methodology for increasing device performance. The ability to create Through Silicon Vias (TSV) provides the shortest path for interconnections and will result in increased device speed and reduced package footprint. There are numerous technical papers and presentations on the etching and filling of these vias, however the process for cleaning is seldom mentioned. Historically, after reactive ion etching (RIE), cleaning is accomplished using an ashing process to remove any remaining photoresist, followed by dipping the wafer in a solution-based post etch residue remover. However, in the case of TSV formation, deep reactive ion etching (DRIE) is used to create the vias. A byproduct of this etching process is the formation of a fluorinated passivation layer, often referred to as a fluoropolymer. The fluoropolymer is not easily removed using traditional post etch residue removers, thus creating the opportunity for new and improved formulations and processes for its removal. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using Dynastrip™ AP7880™-C, coupled with a megasonic final rinse provides clean results for high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001435-001469 ◽  
Author(s):  
Kimberly Pollard ◽  
Meng Guo ◽  
Richie Peters ◽  
Mike Phenis ◽  
Laura Mauer ◽  
...  

The continuing challenge to meet the need for lighter, smaller, faster and smarter electronic systems has pushed the advancement of 2.5D and 3D technology. The ability to create and integrate through-silicon vias (TSV) into device designs in 2.5- and 3-D platforms allows a decrease in interconnection path length, which results in improved device performance and reliability in a small form factor. Mainly due to its high silicon etch rate and selectivity to mask materials, the Bosch process is often used in the TSV fabrication. In this process, the silicon via is created by the deep reactive ion etching (DRIE). DRIE is comprised of repeating a combination of steps: an etch step and a passivation step. The passivation created in the DRIE process results in a fluoropolymer residue remaining on the wafer at the end of the process. The residue must be removed to enable deposition of a defect-free barrier, which enables a defect-free seed layer and void-free plating into the via. There are numerous technical papers and presentations on the etching and filling of these vias but the process for cleaning remains under addressed. Initially, standard processes used after RIE and consisting of an ashing process to remove any remaining photoresist, followed by immersion in a solution-based post etch residue remover were adopted for post-TSV cleans. However, the fluoropolymer does not have the same chemical characteristics as typical post-RIE etch residues and the major challenge has been the difficulty to completely remove it, especially on the via sidewall, using traditional post etches residue removers. Therefore, new formulated cleaning solutions and processes are actively sought for the removal of post etch residue for TSVs. This paper will describe a robust cleaning process for one step removal of both the photoresist and sidewall polymer residues from TSVs. A combination soak and high pressure spray process using a proprietary environmentally friendly chemistry, coupled with a megasonic final rinse provides a unique solution for both polymer residue and photoresist removals on high aspect ratio vias. SEM, EDX and Auger analysis will illustrate the cleanliness levels achieved.


Author(s):  
Ronald Hon ◽  
Shawn X. D. Zhang ◽  
S. W. Ricky Lee

The focus of this study is on the fabrication of through silicon vias (TSV) for three dimensional packaging. According to IPC-6016, the definition of microvias is a hole with a diameter of less than or equal to 150 μm. In order to meet this requirement, laser drilling and deep reactive ion etching (but not wet etching) are used to make the microvias. Comparisons between these two different methods are carried out in terms of wall straightness, smoothness, smallest via produced and time needed for fabrication. In addition, discussion on wafer thinning for making through silicon microvias is given as well.


2008 ◽  
pp. 45-91 ◽  
Author(s):  
Fred Roozeboom ◽  
Michiel A. Blauw ◽  
Yann Lamy ◽  
Eric van Grunsven ◽  
Wouter Dekkers ◽  
...  

Author(s):  
Shawn X. D. Zhang ◽  
Ronald Hon ◽  
S. W. Ricky Lee

Deep reactive ion etching (DRIE) is a major microfabrication process for micro-electro-mechanical system (MEMS) devices. In recent years DRIE is also applied to make through-silicon-vias (TSVs) for 3D packaging. Typical DRIE-formed TSVs are in the range of a few microns to tens of microns. In the present study, silicon vias with diameters in the sub-micron range (0.5 μm and 0.8 μm) are attempted. For comparison purposes, larger silicon vias (1 μm and 3 μm) are fabricated as well. In this paper, the microfabrication processes are described. The experimental results and comparisons in terms of via uniformity, aspect ratio dependent etching, undercutting, and effects of various mask materials are discussed in detail.


2011 ◽  
Vol 21 (10) ◽  
pp. 105001
Author(s):  
Ahmet Erten ◽  
Milan Makale ◽  
Xuekun Lu ◽  
Bernd Fruhberger ◽  
Santosh Kesari ◽  
...  

2017 ◽  
Vol 9 (27) ◽  
pp. 23263-23263
Author(s):  
Bryan W. K. Woo ◽  
Shannon C. Gott ◽  
Ryan A. Peck ◽  
Dong Yan ◽  
Mathias W. Rommelfanger ◽  
...  

Sign in / Sign up

Export Citation Format

Share Document