Signature Restoration for Enhancing Robustness of FPGA IP Designs

2015 ◽  
Vol 9 (3) ◽  
pp. 41-56 ◽  
Author(s):  
Jing Long ◽  
Dafang Zhang ◽  
Wei Liang ◽  
Xia'an Bi
Keyword(s):  
Intellectual Property ◽  
Secret Sharing ◽  
Field Programmable Gate Array ◽  
Sufficient Evidence ◽  
Ip Protection ◽  
Rs Codes ◽  
Field Programmable ◽  
Hardware Resource ◽  
Ip Cores ◽  
Restoration Scheme

Many watermarking techniques for intellectual property (IP) protection are not resilient to tampering or removal attacks, especially for field programmable gate array (FPGA)-based IP cores. If attacked, the damaged watermarks cannot provide sufficient evidence in front of a court. To address this issue, the authors present a signature restoration scheme. The thought of secret sharing is introduced to share the signature into small watermarks. These watermarks are encoded with Reed-Solomon (RS) codes and embedded into unused lookup tables (LUTs) of used slices. Unlike most of existing techniques, the proposed scheme can restore the signature only by extracting parts of watermarks. So, it is tolerant to some damaged watermarks caused by removal attacks. The experiments show that the proposed scheme incurs no extra hardware resource and timing overhead. The robustness against attacks is much better by comparing to other schemes.

The Design and FPGA Implementation of a Polyphase SRRC FIR Filter in DTMB

2013 ◽  
Vol 791-793 ◽  
pp. 2122-2126
Author(s):  
Jing Chen ◽  
Chang Yin Liu ◽  
Xue Ping Li
Keyword(s):  
Field Programmable Gate Array ◽  
Traditional Method ◽  
Sampling Rate ◽  
Digital Signal ◽  
Response Speed ◽  
Fir Filter ◽  
Fir Filters ◽  
Square Root ◽  
Field Programmable ◽  
Hardware Resource

Polyphase FIR filters are applied in many practical Digital Signal Processing applications where the sampling rate needs to be changed. This paper focuses on the implementation of polyphase square root raised cosine (SRRC) FIR filter based on Field Programmable Gate Array (FPGA). The filter employs methods like filter's multiphase structure, symmetrical coefficients, I/Q channel multiplexing, pipeline addition and so on to design the SRRC filter. Compared with the traditional method, the designed FIR filter exhibits the advantages of high response speed and low hardware resource s consumption.

scholarly journals Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 89 ◽  
Author(s):  
Valentina Bianchi ◽  
Marco Bassoli ◽  
Ilaria De Munari
Keyword(s):  
Field Programmable Gate Array ◽  
Rs Codes ◽  
Innovative Method ◽  
Error Magnitude ◽  
Field Programmable ◽  
Theoretical Finding ◽  
Proper Comparison ◽  
Evaluation Module ◽  
Hardware Platforms ◽  
Microcontroller Unit

Reed–Solomon (RS) codes are one of the most used solutions for error correction logic in data communications. RS decoders are composed of several blocks: among them, many efforts have been made to optimize the error magnitude evaluation module. This paper aims to assess the performance of an innovative algorithm introduced in the literature by Lu et al. under different systems configurations and hardware platforms. Several configurations of the encoded message chosen between those typically used in different applications have been designed to be run on an FPGA (field programmable gate array) device and an MCU (microcontroller unit). The performances have been evaluated in terms of resource usage and output delay for the FPGA and in terms of code execution time for the MCU. As a benchmark in the analysis, the well-established Forney’s method is exploited: it has been implemented in the same configurations and on the same hardware platforms for a proper comparison. The results show that the theoretical finding are fully confirmed only in the MCU implementation, while on FPGA, the choice of one method with respect to the other depends on the optimization feature (i.e., time or area) that has been decided as a preference in the specific application.

scholarly journals NIWAS: A non-interactive watermark authentication scheme for industrial field-programmable gate array designs

2018 ◽  
Vol 10 (6) ◽  
pp. 168781401877605 ◽  
Author(s):  
Jing Long ◽  
Dafang Zhang ◽  
Wei Liang ◽  
Zuoting Ning ◽  
Qingyong Zhang
Keyword(s):  
Intellectual Property ◽  
Field Programmable Gate Array ◽  
High Efficiency ◽  
Communication Overhead ◽  
Sensitive Information ◽  
Detection Techniques ◽  
Field Programmable ◽  
Gate Array ◽  
Location Obfuscation ◽  
Intellectual Property Infringement

Except the network attacks, the industrial networked devices in Internet of things are also threatened by intellectual property infringement. Watermarking technique is a prevalent way to avoid this threat. Previous work on authenticating a watermark in industrial intellectual properties easily discloses sensitive information of real embedded watermarks. In this case, the evidence of identifying the ownership of industrial intellectual property may be attacked by the illegal verifiers. Although several watermark detection techniques can address the disclosure of sensitive information in detection procedure, the efficiency of detection is relatively low. Besides, it may yield large communication overhead of multiple authentication rounds. Motivated by the needs of robustness and efficiency, this work proposed a zero-knowledge approach to authenticate ownership of field-programmable gate array intellectual property design in industrial environment, named NIWAS. The prover can convince the verifier that he knows a secret in the suspected intellectual property design via only one interaction. Real locations of watermarks are concealed through location obfuscation. With the received authentication package from the prover, the verifier cannot obtain other useful information about the watermarks. The experiments show that NIWAS achieves high efficiency and robustness of watermark detection.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array
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