CompactRIO Based Real Time Implementation of AES Algorithm for Embedded Applications

2019 ◽  
Vol 10 (2) ◽  
pp. 19-36
Author(s):  
El Adib Samir ◽  
Raissouni Naoufal
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Software Design ◽  
System Architecture ◽  
Advanced Encryption Standard ◽  
Time Cost ◽  
Security Applications ◽  
Aes Algorithm ◽  
Embedded Applications ◽  
Different Levels

For real-time embedded applications, several factors (time, cost, power) that are moving security considerations from a function-centric perspective into a system architecture (hardware/software) design issue. The National Institute of Standards and Technology (NIST) adopts Advanced Encryption Standard (AES) as the most widely used encryption algorithm in many security applications. The AES algorithm specifies 10, 12 and 14 rounds offering different levels of security. Although the number of rounds determines the strength of security, the power consumption issue has risen recently, especially in real-time embedded systems. In this article, the authors present real time implementation of the AES encryption on the compactRIO platform for a different number of AES rounds. The target hardware is NI cRIO-9022 embedded real-time controller from National Instruments (NI). The real time encryption processing has been verified successfully. The power consumption and encryption time experimental results are presented graphically for 10, 12 and 14 rounds of processing.

Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications

2016 ◽  
Vol 25 (07) ◽  
pp. 1650080 ◽  
Author(s):  
Raed Bani-Hani ◽  
Khaldoon Mhaidat ◽  
Salah Harb
Keyword(s):  
Low Power ◽  
Area Ratio ◽  
Advanced Encryption Standard ◽  
Fpga Design ◽  
Power Efficient ◽  
Aes Algorithm ◽  
Lookup Tables ◽  
Small Footprint ◽  
Embedded Applications

In this paper, a very compact and efficient 32-bit FPGA design for the Advanced Encryption Standard (AES) algorithm is presented. The design is very well suited for small foot-print low-power embedded applications. The design is validated and synthesized using the Xilinx ISE Design Suite. To the best of our knowledge, our design is the most efficient in terms of throughput to area ratio and requires the smallest number of lookup tables (LUTs), logic slices, and registers. It also achieves the highest throughput among designs that do not use DSPs. It is also very power-efficient; it can process more than 10 Gbps/W on Kintex-7 FPGA.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 151
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals Speed and Power Consumption Comparison between DES and AES Algorithm in Arduino

2019 ◽  
Vol 6 (1) ◽  
pp. 45-53 ◽  
Author(s):  
Arcelina Sukiatmodjo ◽  
YB Dwi Setianto
Keyword(s):  
Power Consumption ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Average Difference ◽  
Long Distance ◽  
Data Encryption Standard ◽  
Aes Algorithm ◽  
Significant Difference

Telemedicine is commonly used to check or diagnose patients from a long distance. Its application is often combined with sensors as needed, but for delivery, a cryptography algorithm is needed so the data sent safely, illegible, and can not be changed by unauthorized people. Besides that, the algorithm must be light, fast and use less power. In this study, a comparison of the Data Encryption Standard (DES) and Advanced Encryption Standard (AES) algorithms will be implemented in the encryption module. Data from the sensor encrypted and sent to the server. The time and power consumption by DES will be compared with AES. From this research, we can conclude that the encryption time of AES is faster than DES. The average difference speed is 33413 microseconds. Then the power consumption by AES and DES does not have any significant difference, and the addition of sensors causes additional power as well.

scholarly journals A Novel Architecture for Low Power Adiabatic Cipher

2019 ◽  
Vol 8 (4) ◽  
pp. 5619-5623
Keyword(s):  
Data Security ◽  
Advanced Encryption Standard ◽  
Positive Polarity ◽  
Statistical Parameters ◽  
Security Applications ◽  
Adiabatic Logic ◽  
Efficient Charge ◽  
Power Attacks ◽  
Box Method ◽  
Embedded Applications

AES stands for Advanced Encryption Standard. It is widely used in today’s various security applications. S-box method is the most common and important in today’s data security and embedded applications.. This S-box consumes a considerable percentage of power of the whole system. S-box is very prone to differential power attacks(DPA). DPA is the most threatening types of attacks in cryptographic systems. In this paper, we have implemented one positive polarity Reed Muller type S-box is implemented using adiabatic logic. Efficient charge recovery logic(ECRL)is used here. FinFET based ECRL is used to implement the S-box has been observed and calculated .The performance of ECRL based S-box is compared with conventional CMOS based S-box. The statistical parameters for DPA cipher design are also analyzed.

scholarly journals High Speed Area Efficient FPGA Implementation of AES Algorithm

2018 ◽  
Vol 7 (3) ◽  
pp. 157
Author(s):  
P. B. Mane ◽  
A. O. Mulani
Keyword(s):  
Power Consumption ◽  
High Throughput ◽  
High Speed ◽  
Advanced Encryption Standard ◽  
Digital Information ◽  
Unauthorized Access ◽  
Aes Algorithm ◽  
Symmetric Key ◽  
Reconfigurable Platform ◽  
Symmetric Key Cryptography

Now a day digital information is very easy to process, but it allows unauthorized users to access this information. To protect this information from unauthorized access, Advanced Encryption Standard (AES) is one of the most frequently used symmetric key cryptography algorithm. Main objective of this paper is to implement fast and secure AES algorithm on reconfigurable platform. In this paper, AES algorithm is designed with the aim to achieve less power consumption and high throughput. Keys are generated using MATLAB and remaining algorithm is designed using Xilinx SysGen, implemented on Nexys4 and simulated using Simulink. Synthesis result shows that it consumes 121 slice registers and its operating frequency is 1102.536 MHz. Throughput of the overall system is 14.1125 Gbps.

scholarly journals FPGA Implementation of Protected Compact AES S–Box Using CQCG for Embedded Applications

2021 ◽  
Author(s):  
R. Sornalatha ◽  
N. Janakiraman ◽  
K. Balamurugan ◽  
Arun Kumar Sivaraman ◽  
Rajiv Vincent ◽  
...  
Keyword(s):  
Hardware Implementation ◽  
Fpga Implementation ◽  
Advanced Encryption Standard ◽  
Side Channel ◽  
Logic Design ◽  
Substitution Box ◽  
Side Channel Attacks ◽  
Aes Algorithm ◽  
Composite Field ◽  
Embedded Applications

In this work, we obtain an area proficient composite field arithmetic Advanced Encryption Standard (AES) Substitution (S) byte and its inverse logic design. The size of this design is calculated by the number of gates used for hardware implementation. Most of the existing AES Substitution box hardware implementation uses separate Substitution byte and its inverse hardware structures. But we implement the both in the same module and a control signal is used to select the substitution byte for encryption operation and its inverse for the decryption operation. By comparing the gate utilization of the previous AES S–Box implementation, we reduced the gate utilization up to 5% that is we take only 78 EX-OR gates and 36 AND gates for implementing the both Substitution byte and its inverse. While implementing an AES algorithm in circuitry or programming, it is liable to be detected by hackers using any one of the side channel attacks. Data to be added with a random bit sequence to prevent from the above mentioned side channel attacks.

scholarly journals Advanced Encryption Standard for Data Encryption using EDK Environment in FPGA

2019 ◽  
Vol 8 (4) ◽  
pp. 11969-11972
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Data Encryption ◽  
Advanced Encryption Standard ◽  
Gate Arrays ◽  
Aes Algorithm ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Efficient Processing

now a day’s VLSI is developing technology as predicted by Moors law which is drastically increasing as per demand one of that is data security for efficient processing so, data encryption and decryption are major play in security for this an advanced encryption standard is there which uses reconfigurable hardware process in this paper field programmable gate arrays (FPGAs) kit of Xilinx based platform in which spartan3E EDK kit is used. Here we analyze the speed of AES algorithm by using this EDK environment where obvious high speed is considerable and with power consumption and throughput exemptions. With micro blaze soft core processer we implement our algorithm of AES by using c coding we configure the hardware structure. EDK tool with one round operation is done and both area utilization and throughput are observed as we are familiar that when area reduces power consumption also reduces.

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