scholarly journals DESIGN AND INVESTIGATION OF RESISTOR MATRIX FOR ACTIVE ANALOG RC FILTERS

2020 ◽  
Vol 12 (0) ◽  
pp. 1-7
Author(s):  
Leonid Kladovščikov ◽  
Romualdas Navickas
Keyword(s):  
Integrated Circuit ◽  
Design Method ◽  
Process Variations ◽  
Cmos Technology ◽  
Matrix Structure ◽  
Passive Components ◽  
Technology Node ◽  
Self Tuning ◽  
Accurate Comparison ◽  
Tuning Systems

Resistor matrixes are widely used in active RC filters as well as in self-tuning systems. Using self-tuning systems for active RC filters, it is possible to automatically tune various parameters of filter – cut-off frequency, gain and quality of filter. Most recent multiband transceivers employ higher order filters for fine bandpass filtering, thus number of passive components increases. In this work, a novel resistor matrix structure and design method is proposed. Proposed resistor matrix structure compensates both integrated circuit process variations and temperature change. Proposed resistor matrix is designed using 0.18 μm TSMC CMOS technology node and investigated using Cadence Virtuoso software. For most accurate comparison of different resistor matrices, all of them were designed in same technology node using design techniques described in other authors’ works.

scholarly journals Efficient Design for Integrated Photonic Waveguides with Agile Dispersion

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6651
Author(s):  
Zhaonian Wang ◽  
Jiangbing Du ◽  
Weihong Shen ◽  
Jiacheng Liu ◽  
Zuyuan He
Keyword(s):  
Integrated Circuit ◽  
Frequency Comb ◽  
Design Method ◽  
Chromatic Dispersion ◽  
Nonlinear Effects ◽  
Superior Performance ◽  
Efficient Design ◽  
Linear Dispersion ◽  
Dispersion Engineering ◽  
Low Dispersion

Chromatic dispersion engineering of photonic waveguide is of great importance for Photonic Integrated Circuit in broad applications, including on-chip CD compensation, supercontinuum generation, Kerr-comb generation, micro resonator and mode-locked laser. Linear propagation behavior and nonlinear effects of the light wave can be manipulated by engineering CD, in order to manipulate the temporal shape and frequency spectrum. Therefore, agile shapes of dispersion profiles, including typically wideband flat dispersion, are highly desired among various applications. In this study, we demonstrate a novel method for agile dispersion engineering of integrated photonic waveguide. Based on a horizontal double-slot structure, we obtained agile dispersion shapes, including broadband low dispersion, constant dispersion and slope-maintained linear dispersion. The proposed inverse design method is objectively-motivated and automation-supported. Dispersion in the range of 0–1.5 ps/(nm·km) for 861-nm bandwidth has been achieved, which shows superior performance for broadband low dispersion. Numerical simulation of the Kerr frequency comb was carried out utilizing the obtained dispersion shapes and a comb spectrum for 1068-nm bandwidth with a 20-dB power variation was generated. Significant potential for integrated photonic design automation can be expected.

scholarly journals Effects of Process Variations in a HCMOS IC using a Monte Carlo SPICE Simulation

2017 ◽  
pp. 11-16
Author(s):  
Widianto Widianto ◽  
Lailis Syafaah ◽  
Nurhadi Nurhadi
Keyword(s):  
Monte Carlo ◽  
Integrated Circuit ◽  
High Speed ◽  
Evaluation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Process Variations ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Spice Simulation ◽  
Simulation Results

In this paper, effects of process variations in a HCMOS (High-Speed Complementary Metal Oxide Semiconductor) IC (Integrated Circuit) are examined using a Monte Carlo SPICE (Simulation Program with Integrated Circuit Emphasis) simulation. The variations of the IC are L and VTO variations. An evaluation method is used to evaluate the effects of the variations by modeling it using a normal (Gaussian) distribution. The simulation results show that the IC may be detected as a defective IC caused by the variations based on large supply currents flow to it. 

Statistical Gate-Delay Modeling with Copulas

2020 ◽  
Vol 15 (3) ◽  
pp. 1-10
Author(s):  
Walter Schneider
Keyword(s):  
Circuit Design ◽  
Integrated Circuit ◽  
Process Variations ◽  
Deep Submicron ◽  
Experimental Results ◽  
Gate Delay ◽  
Integrated Circuit Design ◽  
Circuit Performance ◽  
Delay Models ◽  
Innovative Concept

The growing impact of process variations on circuit performance has become a major concern for deep-submicron integrated circuit design, resulting in numerous SSTA-algorithms. The acceptance of such algorithms in industry however will be dependent on modeling the real silicon behavior in SSTA. This includes that the statistical gate-delay models must consider arbitrary process variations and dependencies. In this paper, we introduce the innovative concept of Copulas to handle this topic. A complete Matlab based framework starting from process parameter statistics up to the computation of the statistical gate-delay distribution is presented. Experimental results demonstrate the importance of accounting realistic process variations.

Package Voltage Regulators: The Answer for Power Management Challenges

2019 ◽  
Vol 2019 (1) ◽  
pp. 000438-000443 ◽  
Author(s):  
Joseph Meyer ◽  
Reza Moghimi ◽  
Noah Sturcken
Keyword(s):  
Integrated Circuit ◽  
High Performance ◽  
Power Conversion ◽  
Cmos Technology ◽  
Voltage Regulation ◽  
Voltage Regulators ◽  
Electronic Systems ◽  
Single Chip ◽  
Fully Integrated ◽  
Computational Performance

Abstract The generational scaling of CMOS device geometries, as predicted by Moore's law, has significantly outpaced advances in CMOS package and power electronics technology. The conduction of power to a high-performance integrated circuit (IC) die typically requires close to 50% of package and IC I/O and is increasing with trends towards lower supply voltages and higher power density that occur in advanced CMOS nodes. The disparity in scaling of logic, package, and I/O technology has created a significant bottleneck that has become a dominant constraint on computational performance. By performing power conversion and voltage regulation in-package, this limitation can be mitigated. Integration of thin-film ferromagnetic inductors with CMOS technology enables single-chip power converters to be co-packaged with processors, high bandwidth memory (HBM), and/or other modules. This paper highlights the advantages of fully integrated package voltage regulators (PVRs), which include: reducing package I/O allocated for power, eliminating the need for upstream power-conversion stages, and improving transient response. These benefits substantially reduce the size, weight, and power of modern electronic systems.

scholarly journals Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography

2019 ◽  
Vol 3 (4) ◽  
pp. 382-396 ◽  
Author(s):  
Ioannis Karageorgos ◽  
Mehmet M. Isgenc ◽  
Samuel Pagliarini ◽  
Larry Pileggi
Keyword(s):  
Integrated Circuit ◽  
Hardware Implementation ◽  
State Of The Art ◽  
Public Key Cryptography ◽  
Cmos Technology ◽  
Performance Level ◽  
The Other ◽  
Public Key ◽  
Critical Systems ◽  
Software Vulnerabilities

AbstractIn today’s globalized integrated circuit (IC) ecosystem, untrusted foundries are often procured to build critical systems since they offer state-of-the-art silicon with the best performance available. On the other hand, ICs that originate from trusted fabrication cannot match the same performance level since trusted fabrication is often available on legacy nodes. Split-Chip is a dual-IC approach that leverages the performance of an untrusted IC and combines it with the guaranties of a trusted IC. In this paper, we provide a framework for chip-to-chip authentication that can further improve a Split-Chip system by protecting it from attacks that are unique to Split-Chip. A hardware implementation that utilizes an SRAM-based PUF as an identifier and public key cryptography for handshake is discussed. Circuit characteristics are provided, where the trusted IC is designed in a 28-nm CMOS technology and the untrusted IC is designed in an also commercial 16-nm CMOS technology. Most importantly, our solution does not require a processor for performing any of the handshake or cryptography tasks, thus being not susceptible to software vulnerabilities and exploits.

scholarly journals PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 252 ◽  
Author(s):  
Victor Carbajal-Gomez ◽  
Esteban Tlelo-Cuautle ◽  
Carlos Sanchez-Lopez ◽  
Francisco Fernandez-Fernandez
Keyword(s):  
Integrated Circuit ◽  
Secure Communication ◽  
Piecewise Linear ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Chaotic Attractors ◽  
Chaotic Oscillator ◽  
Maximum Lyapunov Exponent ◽  
Chaotic Oscillators ◽  
Cmos Integrated Circuit

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

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