scholarly journals EVALUATION OF VARIOUS COMPILER OPTIMIZATION TECHNIQUES RELATED TO MIBENCH BENCHMARK APPLICATIONS

2013 ◽  
Vol 9 (6) ◽  
pp. 749-756 ◽  
Author(s):  
Andrews
Keyword(s):  
Compiler Optimization ◽  
Optimization Techniques

scholarly journals Lost In Translation: Exposing Hidden Compiler Optimization Opportunities

2020 ◽  
Author(s):  
Kyriakos Georgiou ◽  
Zbigniew Chamski ◽  
Andres Amaya Garcia ◽  
David May ◽  
Kerstin Eder
Keyword(s):  
Compiler Optimization ◽  
Optimization Techniques ◽  
Raspberry Pi ◽  
Routine Testing ◽  
New Approach ◽  
Development Cycle ◽  
Iterative Compilation ◽  
Dependent Potential ◽  
Lost In Translation

Abstract Existing iterative compilation and machine learning-based optimization techniques have been proven very successful in achieving better optimizations than the standard optimization levels of a compiler. However, they were not engineered to support the tuning of a compiler’s optimizer as part of the compiler’s daily development cycle. In this paper, we first establish the required properties that a technique must exhibit to enable such tuning. We then introduce an enhancement to the classic nightly routine testing of compilers, which exhibits all the required properties and thus is capable of driving the improvement and tuning of the compiler’s common optimizer. This is achieved by leveraging resource usage and compilation information collected while systematically exploiting prefixes of the transformations applied at standard optimization levels. Experimental evaluation using the LLVM v6.0.1 compiler demonstrated that the new approach was able to reveal hidden cross-architecture and architecture-dependent potential optimizations on two popular processors: the Intel i5-6300U and the Arm Cortex-A53-based Broadcom BCM2837 used in the Raspberry Pi 3B+. As a case study, we demonstrate how the insights from our approach enabled us to identify and remove a significant shortcoming of the CFG simplification pass of the LLVM v6.0.1 compiler.

scholarly journals Compiler Optimization Techniques for OpenMP Programs

2001 ◽  
Vol 9 (2-3) ◽  
pp. 131-142 ◽  
Author(s):  
Shigehisa Satoh ◽  
Kazuhiro Kusano ◽  
Mitsuhisa Sato
Keyword(s):  
Compiler Optimization ◽  
Distributed Shared Memory ◽  
Memory Systems ◽  
Optimization Techniques ◽  
Dataflow Analysis ◽  
Compiler Optimizations ◽  
Data Dependence Analysis ◽  
Parallel Loops ◽  
Intensive Programs ◽  
Software Distributed Shared Memory

We have developed compiler optimization techniques for explicit parallel programs using the OpenMP API. To enable optimization across threads, we designed dataflow analysis techniques in which interactions between threads are effectively modeled. Structured description of parallelism and relaxed memory consistency in OpenMP make the analyses effective and efficient. We developed algorithms for reaching definitions analysis, memory synchronization analysis, and cross-loop data dependence analysis for parallel loops. Our primary target is compiler-directed software distributed shared memory systems in which aggressive compiler optimizations for software-implemented coherence schemes are crucial to obtaining good performance. We also developed optimizations applicable to general OpenMP implementations, namely redundant barrier removal and privatization of dynamically allocated objects. Experimental results for the coherency optimization show that aggressive compiler optimizations are quite effective for a shared-write intensive program because the coherence-induced communication volume in such a program is much larger than that in shared-read intensive programs.

Analyzing the Feasibility Scheme of Compiler Optimization Techniques for Increasing Efficiency

2018 ◽  
Vol 15 (8) ◽  
pp. 2625-2629
Author(s):  
P Swarnalatha ◽  
Ashish Nagra ◽  
Aryan Rana ◽  
Vatsal Mishra
Keyword(s):  
Compiler Optimization ◽  
Optimization Techniques

scholarly journals Investigating Memory System Energy Behavior Using Software and Hardware Optimizations

VLSI Design ◽  
2001 ◽  
Vol 12 (2) ◽  
pp. 151-165 ◽  
Author(s):  
G. Esakkimuthu ◽  
H. S. Kim ◽  
M. Kandemir ◽  
N. Vijaykrishnan ◽  
M. J. Irwin
Keyword(s):  
Compiler Optimization ◽  
Memory System ◽  
Quantitative Comparison ◽  
Optimization Techniques ◽  
Compiler Optimizations ◽  
Cache Optimization ◽  
Energy Behavior ◽  
Software And Hardware ◽  
System Energy ◽  
Hardware Optimizations

Memory system usually consumes a significant amount of energy in many battery-operated devices. In this paper, we provide a quantitative comparison and evaluation of the interaction of two hardware cache optimization mechanisms and three widely used compiler optimization techniques used to reduce the memory system energy. Our presentation is in two parts. First, we focus on a set of memory-intensive benchmark codes and investigate their memory system energy behavior due to data accesses under hardware and compiler optimizations. Then, using four motion estimation codes, we look at the influence of compiler optimizations on the memory system energy considering the overall impact of instruction and data accesses.

scholarly journals Towards Real-Time DNN Inference on Mobile Platforms with Model Pruning and Compiler Optimization

2020 ◽  
Author(s):  
Wei Niu ◽  
Pu Zhao ◽  
Zheng Zhan ◽  
Xue Lin ◽  
Yanzhi Wang ◽  
...  
Keyword(s):  
Real Time ◽  
Deep Neural Network ◽  
Compiler Optimization ◽  
Super Resolution ◽  
Optimization Techniques ◽  
Mobile Platforms ◽  
Structured Model ◽  
Style Transfer ◽  
Wide Range ◽  
And Storage

High-end mobile platforms rapidly serve as primary computing devices for a wide range of Deep Neural Network (DNN) applications. However, the constrained computation and storage resources on these devices still pose significant challenges for real-time DNN inference executions. To address this problem, we propose a set of hardware-friendly structured model pruning and compiler optimization techniques to accelerate DNN executions on mobile devices. This demo shows that these optimizations can enable real-time mobile execution of multiple DNN applications, including style transfer, DNN coloring and super resolution.

scholarly journals Memory Utilization and Machine Learning Techniques for Compiler Optimization

2021 ◽  
Vol 37 ◽  
pp. 01021
Author(s):  
A V Shreyas Madhav ◽  
Siddarth Singaravel ◽  
A Karmel
Keyword(s):  
Machine Learning ◽  
Low Cost ◽  
Compiler Optimization ◽  
Optimization Methods ◽  
Optimization Techniques ◽  
Machine Learning Techniques ◽  
Peak Performance ◽  
Learning Techniques ◽  
Overall Performance ◽  
Memory Utilization

Compiler optimization techniques allow developers to achieve peak performance with low-cost hardware and are of prime importance in the field of efficient computing strategies. The realm of compiler suites that possess and apply efficient optimization methods provide a wide array of beneficial attributes that help programs execute efficiently with low execution time and minimal memory utilization. Different compilers provide a certain degree of optimization possibilities and applying the appropriate optimization strategies to complex programs can have a significant impact on the overall performance of the system. This paper discusses methods of compiler optimization and covers significant advances in compiler optimization techniques that have been established over the years. This article aims to provide an overall survey of the cache optimization methods, multi memory allocation features and explore the scope of machine learning in compiler optimization to attain a sustainable computing experience for the developer and user.

scholarly journals Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures

2013 ◽  
Vol 2013 ◽  
pp. 1-11 ◽  
Author(s):  
Haijing Tang ◽  
Xu Yang ◽  
Siye Wang ◽  
Yanjun Zhang
Keyword(s):  
Energy Consumption ◽  
Code Generation ◽  
Compiler Optimization ◽  
Instruction Scheduling ◽  
Optimization Techniques ◽  
Generation Process ◽  
Register File ◽  
Access Port ◽  
Common Trend ◽  
Cluster Data

Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explicit inter-cluster data move operations in traditional bus-connected clustered (BCC) VLIW architecture. However, the limit number of access ports to the global register file has become an issue which must be well addressed; otherwise the performance and energy consumption would be harmed. In this paper, we presented compiler optimization techniques for an RFCC VLIW architecture called Lily, which is designed for encryption systems. These techniques aim at optimizing performance and energy consumption for Lily architecture, through appropriate manipulation of the code generation process to maintain a better management of the accesses to the global register file. All the techniques have been implemented and evaluated. The result shows that our techniques can significantly reduce the penalty of performance and energy consumption due to access port limitation of global register file.

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