scholarly journals Comparison of HNN and Ga Based Hybrid Algorithm for Standard Cell Placement in VLSI Design

2016 ◽  
Vol 4 (3) ◽  
pp. 98-101
Author(s):  
Dr. Aaquil Bunglowala ◽  
Dr. Nidhi Asthana
Keyword(s):  
Hybrid System ◽  
Hybrid Algorithm ◽  
Vlsi Design ◽  
Standard Cell ◽  
Wire Length ◽  
Cell Problem ◽  
Cpu Time ◽  
Cell Placement

This research contracts with the notion of hybridization and reports use of hybridizing on GA and HNN. GA and HNN were individually applied to resolve the SCP [3, 4, 5]. In first section we used GA and HNN independently to solve Standard Cell Problem. In the second section we present a new hybrid of GA and HNN. In the last section of the paper we compare the results of hybrid system of GA and HNN with independent result of GA and HNN in respect of wire length and CPU time.

scholarly journals A Swarm Random Walk Based Method for the Standard Cell Placement Problem

2014 ◽  
Vol 2014 ◽  
pp. 1-11 ◽  
Author(s):  
Najwa Altwaijry ◽  
Mohamed El Bachir Menai
Keyword(s):  
Simulated Annealing ◽  
Random Walk ◽  
Hybrid Methods ◽  
Vlsi Design ◽  
Standard Cell ◽  
Placement Problem ◽  
Benchmark Suite ◽  
Cell Placement ◽  
On Chip ◽  
Min Cut

The standard cell placement (SCP) problem is a well-studied placement problem, as it is an important step in the VLSI design process. In SCP, cells are placed on chip to optimize some objectives, such as wirelength or area. The SCP problem is solved using mainly four basic methods: simulated annealing, quadratic placement, min-cut placement, and force-directed placement. These methods are adequate for small chip sizes. Nowadays, chip sizes are very large, and hence, hybrid methods are employed to solve the SCP problem instead of the original methods by themselves. This paper presents a new hybrid method for the SCP problem using a swarm intelligence-based (SI) method, called SwarmRW (swarm random walk), on top of a min-cut based partitioner. The resulting placer, called sPL (swarm placer), was tested on the PEKU benchmark suite and compared with several related placers. The obtained results demonstrate the effectiveness of the proposed approach and show that sPL can achieve competitive performance.

INTERCONNECTION WIRE-LENGTH ESTIMATION IN VLSI STANDARD CELL PLACEMENT VIA NEURAL NETWORK

1998 ◽  
Vol 07 (04) ◽  
pp. 443-451 ◽  
Author(s):  
ASHUTOSH SAXENA ◽  
SUJU M. GEORGE ◽  
P. RAMBABU
Keyword(s):  
Neural Network ◽  
Standard Cell ◽  
Wire Length ◽  
Placement Problem ◽  
Network Characteristics ◽  
Length Estimation ◽  
Input And Output ◽  
The Neural Network ◽  
Cell Placement ◽  
Inaccurate Estimate

Neural Network is used as a tool for estimating interconnection wire-length in VLSI standard cell placement problem. Conventional methods for estimating the interconnection wire-length viz., Bounding Rectangle method, provide inaccurate estimate of the interconnection wire-length and does not depict the interconnection procedure in a layout and separates routing and placement tasks distinctly. The proposed mechanism utilizes the neural network characteristics in understanding the functional mapping between input and output, to estimate the interconnection wire-length. Experiments were performed for different number of cells with varying complexity of interconnections. In all the cases, the performance of the Neural Network is found to be superior to the results obtained using Bounding Rectangle procedure.

Modern Standard-cell Placement Techniques

2001 ◽  
pp. 45-87
Author(s):  
Xiaojian Yang ◽  
Elaheh Bozorgzadeh ◽  
Majid Sarrafzadeh ◽  
Maogang Wang
Keyword(s):  
Standard Cell ◽  
Cell Placement ◽  
Modern Standard
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