scholarly journals DECODING TECHNIQUE FOR LOW POWER DESIGN IN XILINX

2021 ◽  
pp. 261-264
Author(s):  
Rajdip Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Power Design ◽  
Research Paper ◽  
Current Status ◽  
Paper Briefly ◽  
Chip Design ◽  
Research And Practice ◽  
Vlsi Chip ◽  
Low Power System

This research paper is a survey of the current status of research and practice in various disciplines of low power VLSI developments. The paper briefly discusses the rationale of the contemporary, and concentrates on low power design, it presents the metrics and techniques that are used to access the merits of the assorted proposed for the improved energy efficiency. Power dissipation [1], [5] has become an important consideration in terms of performance and scope for VLSI chip design. The research paper describes the decoding strategies, methodology, and techniques for low power system design. Here also we have proposed the decoding technique and compared with silent coding to scale back the transition state and conserved the power which is additionally described during this research. KEYWORDS—Power minimization, decoding technique, silent coding.

scholarly journals Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

2021 ◽  
Vol 12 (2) ◽  
pp. 1628-1633
Author(s):  
Telugu Satyanarayana , Et. al.
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Domino Logic ◽  
Power Circuit ◽  
Vlsi Chip ◽  
Vlsi Technology ◽  
On Chip

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

INTRODUCTION TO LOW-POWER VLSI DESIGN

1996 ◽  
Vol 07 (02) ◽  
pp. 223-248 ◽  
Author(s):  
GARY YEAP ◽  
ANDREAS WILD
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Ad Hoc ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Low Power Design ◽  
Current Status ◽  
Trade Offs ◽  
Device Structures ◽  
The Impact

The paper is a survey of the current status of research and practices in various disciplines of low-power VLSI developments. After briefly discussing the rationale of the contemporary focus on low-power design, it presents the metrics and techniques used to assess the merits of the various solutions proposed for improved energy efficiency. The requirements to be fulfilled by process technologies and device structures are reviewed as well as several promising circuit design styles and ad hoc design techniques. The impact of the design automation tools is analyzed with a special emphasis on physical design and logic synthesis. A review of various architectural trade-offs, including power management, parallelism and pipelining, synchronous versus asynchronous architectures and dataflow transformations are covered, followed by a brief discussion of the impact of the system definition, software and algorithms to the overall power efficiency. Emerging semiconductor technologies and device structures are discussed and the paper is concluded with the trends and research topics for the future.

scholarly journals Addressing Low-Power Electronics in a Digital System and FPGA Design Course

2014 ◽  
Vol 4 (4) ◽  
pp. 33 ◽  
Author(s):  
Marco Winzker
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Power Design ◽  
Digital Design ◽  
Fpga Design ◽  
Sustainable Engineering ◽  
Systems Perspective ◽  
Current Topic ◽  
Low Power Dissipation ◽  
A Current

Low power dissipation is a current topic in digital design, and therefore, it should be covered in a state-of-the-art electrical engineering curriculum. This paper describes how low-power design can be addressed within a digital design course. Doing so would be beneficial for both topics because low-power design is not detached from the systems perspective, and the digital design course would be enriched by references to current challenges and applications. Thus, the presented course should serve as an example of how a course can be developed to also teach students about sustainable engineering.

scholarly journals LOW POWER VLSI TECHNIQUES FOR PORTABLE DEVICES

2020 ◽  
Vol 5 (2) ◽  
pp. 223-232
Author(s):  
Sandeep Singh ◽  
Neeraj Gupta ◽  
Rashmi Gupta
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
Power Dissipation ◽  
Low Power Design ◽  
Vital Role ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Design Strategies ◽  
Power Devices ◽  
Dynamic Power

In the present day scenario, designing a circuit with low power has become very important and challenging task. The designing of any processor for portable devices demands low power. This can be achieved by incorporating low power design strategies and rules at various stages of design. To increase the performance of portable devices, the power backup should be taken in consideration, which is extremely desirable from the users prospective. As we approaches towards the sub-micron technology the requirement of low power devices increases significantly. But at the same time leakage current and dynamic power dissipation play a vital role to diminish the performance of portable devices. This paper presents techniques to reduce the power dissipation and various methodologies to increase the speed of device. That is very beneficial for designing of future VLSI circuits.

Low Power Design of High Speed Communication System Using IO Standard Technique over 28 nm VLSI Chip

2016 ◽  
pp. 323-351
Author(s):  
Bhagwan Das ◽  
Mohammad Faiz Liew Abdullah
Keyword(s):  
Low Power ◽  
Communication System ◽  
Communication Systems ◽  
High Speed ◽  
Vlsi Design ◽  
Low Power Design ◽  
Vlsi Chip ◽  
Vlsi System ◽  
Large Scale Integration ◽  
28 Nm

The low power design of Very Large Scale Integration (VLSI) system is one of the hot topic in research. In this chapter, the low power design for VLSI based high-speed communication is realized over 28 nm VLSI chip packed in UltraScale Field Programming Gate Array (FPGA) using proposed technique. The high-speed communication system is taken as case study for the low power design of VLSI system. Similarly, various VLSI design system can be realized to achieve the low power VLSI system design goal. High-speed communication systems provide the smooth operation for global internet traffic and requires high power devices and components.IO standard is powerful interface tool that provides low power consumption using the fast signal termination by mean of electrical characteristics. In result for this work, more than 96% power reduction is achieved for VLSI based high-speed communication system, when operated at 500 GHZ, 900 GHz, 10 THz and 17 THz carrier frequencies using the High-Speed Unterminated Logic IO Standard. The power analysis is performed using XPA analyzer in Xilinx suite.

AN EFFICIENT LOW-SWING MULTITHRESHOLD-VOLTAGE LOW-POWER DESIGN TECHNIQUE

2004 ◽  
Vol 13 (01) ◽  
pp. 193-203
Author(s):  
A. RJOUB ◽  
M. ALROUSAN ◽  
O. ALJARRAH ◽  
O. KOUFOPAVLOU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Output Voltage ◽  
Supply Voltage ◽  
Low Power Design ◽  
Design Technique ◽  
Cmos Inverter ◽  
Spice Simulation ◽  
Comparison Results ◽  
Simulation Results

New low-power design architecture based on low-swing voltage technique is proposed in this paper. A new CMOS inverter of three output-voltage levels is used to achieve this target. To verify the validity of the proposed technique, three different logic families are used. SPICE simulation results for the three logic families show that more than 45% power dissipation can be saved, without sacrifice the speed operation. Comparison results between the proposed technique and other techniques based on low-swing voltage, shown the superiority of our technique in reducing the power dissipation. Based on 2.4 V supply voltage, a 16 * 16-bit multiplier is implemented by using the proposed technique in 0.25μm silicon technology.

LOW POWER DESIGN OF OFF-CHIP DRIVERS AND TRANSMISSION LINES: A BRANCH AND BOUND APPROACH

1996 ◽  
Vol 07 (02) ◽  
pp. 249-267 ◽  
Author(s):  
ROHINI GUPTA ◽  
JOHN WILLIS ◽  
LAWRENCE T. PILEGGI
Keyword(s):  
Low Power ◽  
Branch And Bound ◽  
Transmission Lines ◽  
Power Dissipation ◽  
Low Power Design ◽  
Driver Model ◽  
Integer Programming Problem ◽  
Enumeration Algorithm ◽  
Line Load ◽  
High Level

As electronic systems grow in functional complexity, hence size, the design is often forced into a multi-chip solution. For such systems, the power dissipation due to the off-chip drivers (OCDs) and the off-chip interconnect capacitance can contribute to a significant portion of the overall system power. Often, however, this excessive power dissipation is unwarranted, since a smaller OCD can be used to drive the transmission line load, hence reducing the net capacitance being switched. The objective of this paper is to enable power dissipation trade-off decisions during the high-level phases of design and to minimize the power dissipation of OCDs and their associated interconnect. First, a termination metric is described that uses width optimization of RLC interconnects. Then, in terms of a proposed linear driver model, the low power design objective is posed as an integer programming problem and a branch and bound enumeration algorithm is presented. The driver and interconnect sizes are determined which will preserve signal quality, dispense with additional termination components, meet delay requirements, and minimize the overall power dissipation.

STATE ENCODING OF FINITE STATE MACHINES FOR LOW POWER DESIGN

1996 ◽  
Vol 06 (06) ◽  
pp. 649-661 ◽  
Author(s):  
DE-SHENG CHEN ◽  
MAJID SARRAFZADEH ◽  
GARY K.H. YEAP
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Finite State Machines ◽  
Low Power Design ◽  
Design Flow ◽  
State Machines ◽  
Switching Activity ◽  
Wide Range ◽  
Finite State ◽  
State Encoding

We address the problem of state encoding for synchronous finite state machines (FSMs), targeted for low power design. Most previous work in FSM state encoding has been focused on minimizing chip area and does not consider switching activity of the circuit. As a result, this does not always lead to a power efficient implementation. Especially in CMOS circuits, the switching activity is a very important factor to power dissipation. In this work, we define a function λ for automatic tradeoff between switching activity and area that contribute to power dissipation. λ is used in determining the encoding affinity between states and is observed to be related to the number of states of an FSM in our experiments. A state encoding algorithm, based on hypercube embedding, is proposed to find encodings of states such that the sum of bit toggles between each pair of states times the encoding affinity between them is minimized. The proposed approach does not require any change in the functional specification of the state machine and can be easily incorporated in present design flow. Results over a wide range of MCNC benchmark examples which show the efficacy of our technique are presented. A simple function for λ is provided, and it is shown to be robust in finding low-power state encodings.

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