scholarly journals Algorithm Level Error Detection in Low Voltage Systolic Array

2021 ◽  
Author(s):  
Mehdi Safarpour
Keyword(s):  
Systolic Array ◽  
Error Detection ◽  
Energy Efficient ◽  
Low Voltage ◽  
Voltage Scaling ◽  
Energy Efficient Architecture ◽  
Algorithm Level

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

scholarly journals Algorithm Level Error Detection in Low Voltage Systolic Array

2021 ◽  
Author(s):  
Mehdi Safarpour
Keyword(s):  
Systolic Array ◽  
Error Detection ◽  
Energy Efficient ◽  
Low Voltage ◽  
Voltage Scaling ◽  
Energy Efficient Architecture ◽  
Algorithm Level

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

scholarly journals Algorithm Level Error Detection in Low Voltage Systolic Array

2021 ◽  
Author(s):  
Mehdi Safarpour ◽  
Reza Inanlou ◽  
Olli Silven
Keyword(s):  
Systolic Array ◽  
Error Detection ◽  
Energy Efficient ◽  
Low Voltage ◽  
Voltage Scaling ◽  
Energy Efficient Architecture ◽  
Algorithm Level

An energy efficient architecture for TPUs that is based on reduced voltage operation. The errors are captured and corrected by utilizing ABFT and hence aggressive voltage scaling is made possible.

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