scholarly journals New approaches to DVFS in mobile MPSoC for power-, thermal-efficiency and reliability

2020 ◽  
Author(s):  
Somdip Dey ◽  
Amit Kumar Singh ◽  
Klaus D. Mcdonald-Maier
Keyword(s):  
System On Chip ◽  
Peak Temperature ◽  
Side Channel ◽  
Performance Requirement ◽  
Different Types ◽  
Dynamic Voltage ◽  
Security And Reliability ◽  
Novel Approaches ◽  
On Chip ◽  
Efficiency And Reliability

<div><div><div><p>Modern mobile devices come equipped with heterogeneous multi-processor system-on-chip (MPSoC) consisting of different types of cores such as CPU and GPU to cater for performance requirement of different types of applications. These MPSoCs also supports dynamic voltage and frequency scaling (DVFS) to reduce dynamic power consumption, which retrospectively affects the peak temperature of the multi-processors on the chip as well. In this poster presentation, we introduce three novel approaches to DVFS in mobile MPSoCs such that the executing applications can meet the performance requirement while consuming less power, reducing peak temperature and improving thermal side-channel security and reliability in terms of lifespan of the device.</p></div></div></div>

scholarly journals New approaches to DVFS in mobile MPSoC for power-, thermal-efficiency and reliability

2020 ◽  
Author(s):  
Somdip Dey ◽  
Amit Kumar Singh ◽  
Klaus D. Mcdonald-Maier
Keyword(s):  
System On Chip ◽  
Peak Temperature ◽  
Side Channel ◽  
Performance Requirement ◽  
Different Types ◽  
Dynamic Voltage ◽  
Security And Reliability ◽  
Novel Approaches ◽  
On Chip ◽  
Efficiency And Reliability

<div><div><div><p>Modern mobile devices come equipped with heterogeneous multi-processor system-on-chip (MPSoC) consisting of different types of cores such as CPU and GPU to cater for performance requirement of different types of applications. These MPSoCs also supports dynamic voltage and frequency scaling (DVFS) to reduce dynamic power consumption, which retrospectively affects the peak temperature of the multi-processors on the chip as well. In this poster presentation, we introduce three novel approaches to DVFS in mobile MPSoCs such that the executing applications can meet the performance requirement while consuming less power, reducing peak temperature and improving thermal side-channel security and reliability in terms of lifespan of the device.</p></div></div></div>

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

scholarly journals How TrustZone Could Be Bypassed: Side-Channel Attacks on a Modern System-on-Chip

2018 ◽  
pp. 93-109 ◽  
Author(s):  
Sebanjila Kevin Bukasa ◽  
Ronan Lashermes ◽  
Hélène Le Bouder ◽  
Jean-Louis Lanet ◽  
Axel Legay
Keyword(s):  
System On Chip ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Modern System ◽  
On Chip

Peak Temperature Minimization for Hard Real-Time Systems Using DVS and DPM

2019 ◽  
Vol 28 (06) ◽  
pp. 1950102
Author(s):  
Mingchuan Zhou ◽  
Long Cheng ◽  
Manuel Dell’Antonio ◽  
Xiebing Wang ◽  
Zhenshan Bing ◽  
...  
Keyword(s):  
Real Time ◽  
Peak Temperature ◽  
Dynamic Power Management ◽  
Real Time Systems ◽  
Dynamic Voltage ◽  
On Chip ◽  
Hard Real Time ◽  
Time Systems ◽  
Power Densities ◽  
Important Design

With the increasing power densities, managing the on-chip temperature has become an important design challenge, especially for hard real-time systems. This paper addresses the problem of minimizing the peak temperature under hard real-time constraints using a combination of dynamic voltage scaling and dynamic power management. We derive a closed-form formulation for the peak temperature and provide a genetic-algorithm-based approach to solve the problem. Our approach is evaluated with both simulations and real measurements with an Intel i5 processor. The evaluation results demonstrate the effectiveness of the proposed approach compared to related works in the literature.

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