scholarly journals Enhancing Q-Factor in a Biquadratic Bandpass Filter Implemented with Opamps

Technologies ◽  
2019 ◽  
Vol 7 (3) ◽  
pp. 64 ◽  
Author(s):  
Esteban Tlelo-Coyotecatl ◽  
Alejandro Díaz-Sánchez ◽  
José Miguel Rocha-Pérez ◽  
Jose Luis Vázquez-González ◽  
Luis Abraham Sánchez-Gaspariano ◽  
...  

Active filter design is a mature topic that provides good solutions that can be implemented using discrete devices or integrated circuit technology. For instance, when the filter topologies are implemented using commercially available operational amplifiers (opamps), one can explore varying circuit parameters to tune the central frequency or enhance the quality (Q) factor. We show the addition of a feedback loop in the signal flow graph of a biquadratic filter topology, which enhances Q and highlights that a sensitivity analysis can be performed to identify which circuit elements influence central frequency, Q, or both. In this manner, we show the opamp-based implementation of a biquadratic bandpass filter, in which Q is enhanced through performing a sensitivity analysis for each circuit element. Equations for the central frequency and Q are provided to observe that there is not a direct parameter that enhances them, but we show that from sensitivity analysis one can identify the circuit elements that better enhance Q-factor.

2014 ◽  
Vol 23 (02) ◽  
pp. 1450016
Author(s):  
JIANLI CHEN ◽  
WENXING ZHU

The very large-scale integrated circuit (VLSI) placement problem is to determine the exact location of each movable circuit element within a given region. It is a crucial process in physical design, since it affects performance, power consumption, routability, and heat distribution of a design. In this paper, we propose a VLSI placement flow to handle the large-scale mixed-size placement problem. The main idea of our placement flow is using a floorplanning algorithm to guide the placement of circuit elements. It consists of four steps: (1) With the multilevel framework, circuit elements are clustered into blocks by recursively partitioning; (2) a floorplanning algorithm is performed on every level of the blocks; (3) the macro cells are shifted by a macro shifting technique to determine their exact locations; (4) with each macro cell location fixed, a standard cell placement algorithm is applied to place the remaining objects. The proposed approach is tested on the IBM mixed-size benchmarks and the modern mixed-size (MMS) placement benchmarks. Experimental results show that our approach outperforms the state-of-the-art placers on the solution quality for most of the benchmarks.


Author(s):  
E. Edwar ◽  
M.R. Yusron ◽  
Dharu Arseno

Filter is an important part in telecommunication system including in radar system. To get the better performance in selecting the signal, a ftlter must have a good Q-Factor. In this paper, an investigation of a ftlter design for synthetic radar has been successfully done. This ftlter has been designed to work at x-band using square loop resonator (SLR). A Defected Ground Structure (DGS) has been implemented to this work to increase the Q-factor of the ftlter. The result of measurement getting that the center frequency at 9.51 GHz with the bandwidth 610 MHz and PCB size of this ftlter is 22 mm x 16 mm.


Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.


Author(s):  
Lukman Medriavin Silalahi ◽  
Setiyo Budiyanto ◽  
Imelda Uli Vistalina Simanjuntak ◽  
Freddy Artadima Silaban ◽  
Nofal Gusti Sulissetyo ◽  
...  

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