scholarly journals Operation of a UXE-Type 11-Level Inverter with Voltage-Balance Modulation Using NLC and ACO-Based SHE

2021 ◽  
Vol 13 (16) ◽  
pp. 9035
Author(s):  
Mohammad Ali ◽  
Mohd Tariq ◽  
Chang-Hua Lin ◽  
Ripon K. Chakrobortty ◽  
Basem Alamri ◽  
...  
Keyword(s):  
Ant Colony Optimization ◽  
Direct Current ◽  
Control Algorithm ◽  
Ant Colony ◽  
Hardware In The Loop ◽  
Level Control ◽  
Harmonic Elimination ◽  
Selective Harmonic Elimination ◽  
Voltage Balance ◽  
Redundant States

In this article, the UXE-Type inverter is considered for eleven-level operation. This topology exhibits a boosting capability along with reduced switches and one source. An algorithm that utilizes the redundant states to control the voltage-balance of the auxiliary direct current (DC)-link is presented. The proposed control algorithm is capable of maintaining the voltages of each capacitor at Vdc/4 resulting in a successful multilevel operation for all values of load. The inverter is also compared with 11-level inverters. The modulation of the inverter is performed by employing nearest level control and ant colony optimization based selective harmonic elimination. The maximum inverter efficiency is 98.1% and its performance is validated on an hardware-in-the-loop platform.

scholarly journals Selective Harmonic Elimination Based THD Minimization of a Symmetric 9-Level Inverter Using Ant Colony Optimization

2021 ◽  
Vol 8 (5) ◽  
pp. 769-774
Author(s):  
Neerudi Bhoopal ◽  
Dokku Sivanaga Malleswara Rao ◽  
Bharath Kumar Narukullapati ◽  
Idamakanti Kasireddy ◽  
Devineni Gireesh Kumar
Keyword(s):  
Ant Colony Optimization ◽  
Single Phase ◽  
Frequency Control ◽  
Harmonic Distortion ◽  
Low Frequency ◽  
Ant Colony ◽  
Medium Voltage ◽  
Semiconductor Switches ◽  
Harmonic Elimination ◽  
Selective Harmonic Elimination

This paper proposed a new topology of a symmetric single-phase multilevel inverter with the smaller number of semiconductor switches and optimized low-frequency control methods to optimize the Total Harmonic Distortion. A nine-level single phase output is obtained by eight number of active semiconductor switches, four diodes and four capacitors from two asymmetrical dc sources. The selected harmonic order in the output voltage is eliminated by the PWM (SHE-PWM) based on selective harmonic elimination. To optimize the switching angles, an ant colony optimization is introduced. The proposed SHE-PWM and ant optimization are implemented and tested for THD on the SIMULINK platform. The proposed approach offers less THD and is best suited to high-power applications with medium voltage.

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