scholarly journals Ultra-Low Power Hand Gesture Sensor Using Electrostatic Induction

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8268
Author(s):  
Hiroshi Fuketa
Keyword(s):  
Low Power ◽  
Gesture Recognition ◽  
Complementary Metal Oxide Semiconductor ◽  
Hand Gesture Recognition ◽  
Oxide Semiconductor ◽  
Hand Movements ◽  
Hand Gesture ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Electrostatic Induction

This paper presents an ultra-low power hand gesture sensor using electrostatic induction for mobile devices. Two electrodes, which consist of electret foils stacked on metal sheets, are used to recognize two gestures such as hand movements from left to right and right to left. The hand gesture recognition is realized by detecting the electrostatic induction currents induced by hand movements. However, the electrostatic induction currents are significantly small; hence, a hand gesture recognition chip is first designed in this study to amplify and detect the small electrostatic induction currents with low power. This chip is fabricated in a commercial 180 nm complementary metal oxide semiconductor (CMOS) process, and the measurement results indicate that the fabricated gesture recognition chip consumes 406 nW, which is less than 1/100th of the power dissipation of conventional gesture sensors.

scholarly journals To Control Electrical MCBs using Hand Gesture Recognition

2015 ◽  
Vol 14 (9) ◽  
pp. 6102-6106
Author(s):  
Sangeeta Goyal ◽  
Dr. Bhupesh Kumar
Keyword(s):  
Human Computer Interaction ◽  
Gesture Recognition ◽  
Human Body ◽  
Circuit Breaker ◽  
Hand Gesture Recognition ◽  
Hand Movements ◽  
Hand Gesture ◽  
Handicapped Person ◽  
New Techniques ◽  
Computer Interaction

There has been growing interest in development of new techniques and methods for Human-Computer Interaction (HCI). Gesture Recognition is one of the important areas of this technology. Gesture Recognition means interfacing with computer using motion of human body typically hand movements. As a Handicapped person cannot move very easily and quickly if there is a fire in house or he/she cannot switch off the Miniature Circuit Breaker (MCB) but the same task can be done easily with hand gesture recognition. In our proposed system electrical MCB can be controlled using hand gesture recognizer. To switch on/off the MCB, we need to provide hand based gesture as an input to system.

scholarly journals An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1760
Author(s):  
Folla Kamdem Jérôme ◽  
Wembe Tafo Evariste ◽  
Essimbi Zobo Bernard ◽  
Maria Liz Crespo ◽  
Andres Cicuttin ◽  
...  
Keyword(s):  
Low Power ◽  
High Throughput ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
High Luminosity ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Ultra Low Power ◽  
Front End

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

scholarly journals Memristive and CMOS Devices for Neuromorphic Computing

Materials ◽  
2020 ◽  
Vol 13 (1) ◽  
pp. 166 ◽  
Author(s):  
Valerio Milo ◽  
Gerardo Malavena ◽  
Christian Monzio Compagnoni ◽  
Daniele Ielmini
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Low Power ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Neuromorphic Computing ◽  
Ultra Low Power ◽  
Von Neumann ◽  
Novel Device ◽  
Von Neumann Architecture

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

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