scholarly journals Modeling, Simulation Methods and Characterization of Photon Detection Probability in CMOS-SPAD

Sensors ◽  
2021 ◽  
Vol 21 (17) ◽  
pp. 5860
Author(s):  
Aymeric Panglosse ◽  
Philippe Martin-Gonthier ◽  
Olivier Marcelot ◽  
Cédric Virmontois ◽  
Olivier Saint-Pé ◽  
...  
Keyword(s):  
Detection Probability ◽  
Computer Aided Design ◽  
Single Photon ◽  
Complementary Metal Oxide Semiconductor ◽  
Simulation Method ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Doping Profile ◽  
Cmos Process ◽  
Photon Detection

Single-Photon Avalanche Diodes (SPAD) in Complementary Metal-Oxide Semiconductor (CMOS) technology are potential candidates for future “Light Detection and Ranging” (Lidar) space systems. Among the SPAD performance parameters, the Photon Detection Probability (PDP) is one of the principal parameters. Indeed, this parameter is used to evaluate the SPAD sensitivity, which directly affects the laser power or the telescope diameter of space-borne Lidars. In this work, we developed a model and a simulation method to predict accurately the PDP of CMOS SPAD, based on a combination of measurements to acquire the CMOS process doping profile, Technology Computer-Aided Design (TCAD) simulations, and a Matlab routine. We compare our simulation results with a SPAD designed and processed in CMOS 180 nm technology. Our results show good agreement between PDP predictions and measurements, with a mean error around 18.5%, for wavelength between 450 and 950 nm and for a typical range of excess voltages between 15 and 30% of the breakdown voltage. Due to our SPAD architecture, the high field region is not entirely insulated from the substrate, a comparison between simulations performed with and without the substrate contribution indicates that PDP can be simulated without this latter with a moderate loss of precision, around 4.5 percentage points.

scholarly journals Photon-Detection-Probability Simulation Method for CMOS Single-Photon Avalanche Diodes

Sensors ◽  
2020 ◽  
Vol 20 (2) ◽  
pp. 436 ◽  
Author(s):  
Chin-An Hsieh ◽  
Chia-Ming Tsai ◽  
Bing-Yue Tsui ◽  
Bo-Jen Hsiao ◽  
Sheng-Di Lin
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Photons ◽  
Photon Detection ◽  
Important Indicator ◽  
Avalanche Diodes ◽  
Single Photon Avalanche Diodes

Single-photon avalanche diodes (SPADs) in complementary metal-oxide-semiconductor (CMOS) technology have excellent timing resolution and are capable to detect single photons. The most important indicator for its sensitivity, photon-detection probability (PDP), defines the probability of a successful detection for a single incident photon. To optimize PDP is a cost- and time-consuming task due to the complicated and expensive CMOS process. In this work, we have developed a simulation procedure to predict the PDP without any fitting parameter. With the given process parameters, our method combines the process, the electrical, and the optical simulations in commercially available software and the calculation of breakdown trigger probability. The simulation results have been compared with the experimental data conducted in an 800-nm CMOS technology and obtained a good consistence at the wavelength longer than 600 nm. The possible reasons for the disagreement at the short wavelength have been discussed. Our work provides an effective way to optimize the PDP of a SPAD prior to its fabrication.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  
Keyword(s):  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Sar Adc ◽  
Oxide Semiconductor ◽  
Power Measurement ◽  
Cmos Process ◽  
Analog To Digital ◽  
Full Speed ◽  
Time Interleaved

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.

scholarly journals Current-Assisted SPAD with Improved p-n Junction and Enhanced NIR Performance

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7105
Author(s):  
Gobinath Jegannathan ◽  
Thomas Van den Dries ◽  
Maarten Kuijk
Keyword(s):  
Detection Probability ◽  
Single Photon ◽  
Central Area ◽  
Timing Jitter ◽  
Photon Absorption ◽  
Cmos Process ◽  
Photon Detection ◽  
Drift Field ◽  
Absorption Area ◽  
Improved Performance

Single-photon avalanche diodes (SPADs) fabricated in conventional CMOS processes typically have limited near infra-red (NIR) sensitivity. This is the consequence of isolating the SPADs in a lowly-doped deep N-type well. In this work, we present a second improved version of the “current-assisted” single-photon avalanche diode, fabricated in a conventional 350 nm CMOS process, having good NIR sensitivity owing to 14 μm thick epilayer for photon absorption. The presented device has a photon absorption area of 30 × 30 µm2, with a much smaller central active area for avalanche multiplication. The photo-electrons generated in the absorption area are guided swiftly towards the central area with a drift field created by the “current-assistance” principle. The central active avalanche area has a cylindrical p-n junction as opposed to the square geometry from the previous iteration. The presented device shows improved performance in all aspects, most notably in photon detection probability. The p-n junction capacitance is estimated to be ~1 fF and on-chip passive quenching with source followers is employed to conserve the small capacitance for bringing monitoring signals off-chip. Device physics simulations are presented along with measured dark count rate (DCR), timing jitter, after-pulsing probability (APP) and photon detection probability (PDP). The presented device has a peak PDP of 22.2% at a wavelength of 600 nm and a timing jitter of 220 ps at a wavelength of 750 nm.

A speed-optimized, low-noise APD with 0.18 μm CMOS technology for the VLC applications

2020 ◽  
Vol 34 (29) ◽  
pp. 2050321
Author(s):  
Wei Wang ◽  
Hong-An Zeng ◽  
Fang Wang ◽  
Guanyu Wang ◽  
Yingtao Xie ◽  
...  
Keyword(s):  
Dark Current ◽  
Complementary Metal Oxide Semiconductor ◽  
Visible Light Communication ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Excess Noise ◽  
Avalanche Breakdown ◽  
Cmos Process ◽  
Noise Characteristics

A new avalanche photodiode device applied to a visible light communication (VLC) system is designed using a standard 0.18 [Formula: see text]m complementary metal oxide semiconductor process. Compared to regular CMOS APD devices, the proposed device adds a [Formula: see text]-well layer above the deep [Formula: see text]-well/[Formula: see text]-substrate structure, and an [Formula: see text]/[Formula: see text] layer is deposited upon it. The [Formula: see text]/[Formula: see text] layer acts as an avalanche breakdown layer of the device, and an STI structure is used to prevent the edge break prematurely. The simulation results shows that the avalanche breakdown voltage is as low as 9.9 V, dark current is below [Formula: see text] A under −9.5 V bias voltage, and the 3 dB bandwidth is of 5.9 GHz. It is due to the use of the 0.18 [Formula: see text]m CMOS process-specific STI protection ring and short-circuits the connection of the deep [Formula: see text]-well/[Formula: see text]-substrate, and the dark current is reduced to be lower than two orders of magnitude compared to regular CMOS APD. Gain and noise characteristics are accurately calculated from Hayat dead-space model applied to this CMOS APD. So, this device’s gain and excess noise factor are 20 and 2.5, respectively.

Fabrication of microbridges in standard complementary metal oxide semiconductor technology

1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Layout Design ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Digital Cmos ◽  
Sensor Applications

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.

A Novel Structure of Thermopile Infrared Detector with High Responsivity Based on CMOS Process

2012 ◽  
Vol 271-272 ◽  
pp. 381-385
Author(s):  
Lei Sun ◽  
Wei Bing Wang ◽  
Xiao Yong Fang
Keyword(s):  
Infrared Detector ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Consumer Products ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Ir Detector ◽  
Additional Material ◽  
High Responsivity ◽  
Novel Structure

Superscript textThermopile-type Infrared detector is more and more popular in many fields, including infrared spectroscopy, radiometry, security systems and many consumer products. This paper reports a novel n-poly/p-poly thermopile suspension structure with four pairs of thermopiles that compatible with Complementary Metal-Oxide Semiconductor (CMOS) technology and its fill factor is larger than 90%. No additional material is needed to enhance infrared absorption since the passivation layer provided by the CMOS process is sufficient for certain infrared spectral bands. With the selected material parameters the optimal structure parameters are obtained after simulation. Through the theoretic calculation, this novel IR detector has good properties of high responsivity (larger than 1000V/W) and detectivity (larger than 1×108cm Hz1/2W-1) and low response time (shorter than 30ms).

Compatibility Challenges for High-ĸ Materials Integration into CMOS Technology

MRS Bulletin ◽  
2002 ◽  
Vol 27 (3) ◽  
pp. 226-229 ◽  
Author(s):  
Supratik Guha ◽  
Evgeni Gusev ◽  
Matthew Copel ◽  
Lars-Åke Ragnarsson ◽  
Douglas A. Buchanan
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Electrical Performance ◽  
Cmos Process ◽  
High Q ◽  
Materials Integration ◽  
Technical Requirements ◽  
Scientists And Engineers ◽  
Performance Challenges

AbstractIn addition to meeting the formidable challenges of replacing the nearly perfect SiO2 dielectric, a new dielectric ideally needs to replace SiO2 with minimal rearrangement of the complementary metal oxide semiconductor (CMOS) process flow. In this article, we outline the essential materials-integration issues that arise out of the technical requirements for minimizing changes to future process technologies. These include interfacial layer formation, film microstructure, deposition technologies, and electrical performance challenges such as trapped charge and the mobility degradation associated with any replacement material. Integration of the high-ĸ materials currently under consideration presents a significant challenge for materials scientists and engineers in industry and academia.

scholarly journals Monolithically-Integrated Single-Photon Avalanche Diode in a Zero-Change Standard CMOS Process for Low-Cost and Low-Voltage LiDAR Application

Instruments ◽  
2019 ◽  
Vol 3 (2) ◽  
pp. 33
Author(s):  
Jinsoo Rhim ◽  
Xiaoge Zeng ◽  
Zhihong Huang ◽  
Sai Rahul Chalamalasetti ◽  
Marco Fiorentino ◽  
...  
Keyword(s):  
Low Voltage ◽  
Single Photon ◽  
Low Cost ◽  
Minimum Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Complete Characterization ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Avalanche Diode ◽  
Monolithically Integrated

We present a single-photon sensor based on the single-photon avalanche diode (SPAD) that is suitable for low-cost and low-voltage light detection and ranging (LiDAR) applications. It is implemented in a zero-change standard 0.18-μm complementary metal oxide semiconductor process at the minimum cost by excluding any additional processing step for customized doping profiles. The SPAD is based on circular shaped P+/N-well junction of 8-μm diameter, and it achieves low breakdown voltage below 10 V so that the operation voltage of the single-photon sensor can be minimized. The quenching and reset circuit is integrated monolithically to capture photon-generated output pulses for measurement. A complete characterization of our single-photon sensor is provided.

scholarly journals Micro Magnetic Field Sensors Manufactured Using a Standard 0.18-μm CMOS Process

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 393 ◽  
Author(s):  
Yen-Nan Lin ◽  
Ching-Liang Dai
Keyword(s):  
Magnetic Field ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Magnetic Field Sensors ◽  
Sensor Sensitivity ◽  
Sensor Fabrication ◽  
The Magnetic Field ◽  
Hall Elements

Micro magnetic field (MMF) sensors developed employing complementary metal oxide semiconductor (CMOS) technology are investigated. The MMF sensors, which are a three-axis sensing type, include a magnetotransistor and four Hall elements. The magnetotransistor is utilized to detect the magnetic field (MF) in the x-axis and y-axis, and four Hall elements are used to sense MF in the z-axis. In addition to emitter, bases and collectors, additional collectors are added to the magnetotransistor. The additional collectors enhance bias current and carrier number, so that the sensor sensitivity is enlarged. The MMF sensor fabrication is easy because it does not require post-CMOS processing. Experiments depict that the MMF sensor sensitivity is 0.69 V/T in the x-axis MF and its sensitivity is 0.55 V/T in the y-axis MF.

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