scholarly journals Low-Power Wireless Data Transfer System for Stimulation in an Intracortical Visual Prosthesis

Sensors ◽  
2021 ◽  
Vol 21 (3) ◽  
pp. 735
Author(s):  
Adedayo Omisakin ◽  
Rob M. C. Mestrom ◽  
Mark J. Bentum
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
Carrier Frequency ◽  
Data Transfer ◽  
Data Communication ◽  
Data Rate ◽  
Visual Prosthesis ◽  
Digital Architecture ◽  
Implanted Electrodes

There is a growing interest to improve the quality of life of blind people. An implanted intracortical prosthesis could be the last resort in many cases of visual impairment. Technology at this moment is at a stage that implementation is at sight. Making the data communication to and from the implanted electrodes wireless is beneficial to avoid infection and to ease mobility. Here, we focus on the stimulation side, or downlink, for which we propose a low-power non-coherent digital demodulator on the implanted receiver. The experimentally demonstrated downlink is on a scaled-down version at a 1 MHz carrier frequency showing a data rate of 125 kbps. This provides proof of principle for the system with a 12 MHz carrier frequency and a data rate of 4 Mbps, which consumes under 1 mW at the receiver side in integrated circuit (IC) simulation. Due to its digital architecture, the system is easily adjustable to an ISM frequency band with its power consumption scaling linearly with the carrier frequency. The tested system uses off-the-shelf coils, which gave sufficient bandwidth, while staying within safe SAR limits. The digital receiver achieved a reduction in power consumption by skipping clock cycles of redundant bits. The system shows a promising pathway to a low-power wireless-enabled visual prosthesis.

A GaAs monolithic amplifier with extremely low power consumption

1991 ◽  
Vol 69 (3-4) ◽  
pp. 177-179
Author(s):  
Langis Roy ◽  
Malcolm G. Stubbs ◽  
James S. Wight
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Gain ◽  
Low Power Consumption ◽  
Monolithic Microwave Integrated Circuit ◽  
Dc Power ◽  
Broadband Amplifier ◽  
Effect Transistor ◽  
And Performance

The design and performance of a high-gain, monolithic, broadband amplifier with extremely low power consumption are described. The amplifier, fabricated using a 0.5 μm GaAs depletion-mode MESFET (metal semiconductor field effect transistor) process, utilizes very small gate width devices to achieve a measured gain of 19 dB and a 0.1 to 2.1 GHz bandwidth with only 63 mW dc power dissipation. This is the lowest power consumption broadband MMIC (monolithic microwave integrated circuit) reported to date and is intended for mobile radio applications.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

scholarly journals Adaptive-speed/CAV algorithm in a CD-ROM drive to accomplish high data transfer rate and low power consumption

1998 ◽  
Vol 34 (2) ◽  
pp. 407-410
Author(s):  
S.G. Stan ◽  
H. Van Kempen ◽  
C.-C.S. Lin ◽  
M.-S.M. Yen ◽  
W.W. Wang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Transfer Rate ◽  
Data Transfer ◽  
Low Power Consumption ◽  
Data Transfer Rate ◽  
Cd Rom ◽  
High Data

Tunable Low Power UWB Transmitter for WBAN Application

2015 ◽  
Vol 24 (03) ◽  
pp. 1550040 ◽  
Author(s):  
V. Vinod Kumar ◽  
M. Meenakshi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Efficiency ◽  
Delay Line ◽  
Data Transfer ◽  
Low Cost ◽  
Wireless Body Area Network ◽  
Superior Performance ◽  
Area Network ◽  
Coverage Area

This paper presents the design and simulation results for a Federal Communication Committee (FCC) complaint current starved delay line based Ultra Wide Band (UWB) Gaussian pulse transmitter, which is designed for operating in the 3.1–10.6 GHz range. The wavelet is a mono cycle Gaussian impulse wave, which is practically well suited for low cost, low power, low data rate wireless data transfer such as in wireless body area network (WBAN) applications. The transmitter operating frequency and bandwidth (BW) is controlled using a dc voltage provided at the input stage of a voltage controlled delay line (VCDL) and this aspect can be exploited for increasing the communication coverage area without compromising on the power consumption. A Gaussian wave shaping is performed for FCC compliance and the simulation has been carried out with 130 nm technology. The simulation of our design suggests an average dynamic power consumption of 1.11 mw for an energy efficiency of 14.2 pJ/pulse. The proposed IR-UWB transmitter design though a bit inferior in terms of the power efficiency, can claim superior performance with respect to tuning the BW, which is very relevant in a cognitive wireless networking scenario with other interfering signals.

scholarly journals Sub-Milliwatt Transceiver IC for Transcutaneous Communication of an Intracortical Visual Prosthesis

Electronics ◽  
2021 ◽  
Vol 11 (1) ◽  
pp. 24
Author(s):  
Adedayo Omisakin ◽  
Rob Mestrom ◽  
Georgi Radulov ◽  
Mark Bentum
Keyword(s):  
Low Power ◽  
Integrated Circuit ◽  
Cmos Technology ◽  
Vital Role ◽  
Visual Prosthesis ◽  
Outer Side ◽  
Test Chip ◽  
Wireless Links ◽  
Budget Analysis ◽  
Shift Keying

An intracortical visual prosthesis plays a vital role in partially restoring the faculty of sight in visually impaired people. Reliable high date rate wireless links are needed for transcutaneous communication. Such wireless communication should receive stimulation data (downlink) and send out neural recorded data (uplink). Hence, there is a need for an implanted transceiver that is low-power and delivers sufficient data rate for both uplink and downlink. In this paper, we propose an integrated circuit (IC) solution based on impulse radio ultrawideband using on-off keying modulation (OOK IR-UWB) for the uplink transmitter, and binary phase-shift keying (BPSK) with sampling and digital detection for the downlink receiver. To make the solution low-power, predominantly digital components are used in the presented transceiver test-chip. Current-controlled oscillators and an impulse generator provide tunability and complete the on-chip integration. The transceiver test-IC is fabricated in 180 nm CMOS technology and occupies only 0.0272 mm2. At 1.3 V power supply, only 0.2 mW is consumed for the BPSK receiver and 0.3 mW for the IR-UWB transmitter in the transceiver IC, while delivering 1 Mbps and 50 Mbps, respectively. Our link budget analysis shows that this test chip is suitable for intracortical integration considering the future off-chip antennas/coils transcutaneous 3–7 mm communication with the outer side. Hence, our work will enable realistic wireless links for the intracortical visual prosthesis.

Design of DQPSK Demodulator for Implantable Biomedical Devices

2020 ◽  
Vol 29 (11) ◽  
pp. 2020007
Author(s):  
Vaibhav Garg ◽  
Kavindra Kandpal
Keyword(s):  
Low Power ◽  
Carrier Frequency ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Vital Role ◽  
Data Rate ◽  
High Data Rate ◽  
Biomedical Devices ◽  
High Data ◽  
Implantable Biomedical Devices

Implantable biomedical devices (IBDs) play a vital role in today’s healthcare industry. Such applications demand high data rate, low power and small-sized demodulators. This work presents a simple small-sized low-power architecture for differential quadrature phase shift keying (DQPSK) demodulator for these devices. The proposed circuitry is designed in UMC 90-nm CMOS technology and occupies a layout area of 0.015[Formula: see text]mm2. It is operated at 1-V supply voltage with a power consumption of 405[Formula: see text][Formula: see text]W. The carrier frequency is 10[Formula: see text]MHz and the obtained data rate is 20[Formula: see text]Mbps. Hence it exhibits a high data-rate-to-carrier-frequency (DRCF) ratio of 200% making it ideal for IBDs.

SMALL-SCALE InGaP/GaAs HETEROJUNCTION BIPOLAR TRANSISTORS FOR HIGH-SPEED AND LOW-POWER INTEGRATED-CIRCUIT APPLICATIONS

2001 ◽  
Vol 11 (01) ◽  
pp. 115-136 ◽  
Author(s):  
TOHRU OKA ◽  
KOJI HIRATA ◽  
HIDEYUKI SUZUKI ◽  
KIYOSHI OUCHI ◽  
HIROYUKI UCHIYAMA ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Heterojunction Bipolar Transistors ◽  
Integrated Circuit ◽  
High Speed ◽  
Bipolar Transistors ◽  
Small Scale ◽  
Flip Flop ◽  
Base Electrode ◽  
Power Integrated Circuit

Small-scale InGaP/GaAs heterojunction bipolar transistors (HBTs) with high-speed as well as low-current operation are demonstrated. To reduce the emitter size SE and the base-collector capacitance CBC simultaneously, the HBTs are fabricated by using WSi/Ti as the base electrode and by burying SiO 2 in the extrinsic collector region. WSi/Ti metals simplify and facilitate processing to fabricate small base electrodes, and the buried SiO 2 reduces the parasitic CBC under the base electrode. The cutoff frequency fT of 156 GHz and the maximum oscillation frequency f max of 255 GHz were obtained at a collector current Ic of 3.5 mA for the HBT with SE of 0.5 μ m ×4.5 μ m , and fT of 114 GHz and f max of 230 GHz were obtained at IC of 0.9 mA for the HBT with SE of 0.25 μ m ×1.5 μ m . A 1/8 static frequency divider operated at a maximum toggle frequency of 39.5 GHz with a power consumption per flip-flop of 190 mW. A transimpedance amplifier provides a gain of 46.5 dB·Ω with a bandwidth of 41.6 GHz at a power consumption of 150 mW. These results indicate the great potential of our HBTs for high-speed. low power integrated circuit applications.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

Sign in / Sign up

Export Citation Format

Share Document