scholarly journals Categorization and Characterization of Time Domain CMOS Temperature Sensors

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6700
Author(s):  
Sangjin Byun
Keyword(s):  
Time Domain ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Temperature Sensors ◽  
Oxide Semiconductor ◽  
Voltage Sensitivity ◽  
Power Supply Voltage ◽  
Measured Time ◽  
Long Time ◽  
The Time Domain

Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.

scholarly journals Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  
Keyword(s):  
Nonvolatile Memory ◽  
High Speed ◽  
Low Voltage ◽  
Supply Voltage ◽  
Random Access ◽  
Magnetic Tunnel Junction ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

scholarly journals Calibration of ultrasonic hardware for enhanced total focusing method imaging

2020 ◽  
Vol 62 (7) ◽  
pp. 408-415
Author(s):  
M Ingram ◽  
A Gachagan ◽  
A Nordon ◽  
A J Mulholland ◽  
M Hegarty
Keyword(s):  
Time Domain ◽  
Pressure Profile ◽  
Side Lobe ◽  
Destructive Testing ◽  
Experimental Variation ◽  
Focal Position ◽  
Measured Time ◽  
The Time Domain ◽  
Ray Path ◽  
The Impact

Experimental variation from ultrasonic hardware is one source of uncertainty in measured ultrasonic data. This uncertainty leads to a reduction in the accuracy of images generated from these data. In this paper, a quick, easy-to-use and robust methodology is proposed to reduce this uncertainty in images generated using the total focusing method (TFM). Using a 128-element linear phased array, multiple full matrix capture (FMC) datasets of a planar reflection are used to characterise the experimental variation associated with each element index in the aperture. Following this, a methodology to decouple the time-domain error associated with transmission and reception at each element index is presented. These time-domain errors are then introduced into a simulated array model used to generate the two-way pressure profile from the array. The side-lobe-to-main-lobe energy ratio (SMER) and beam offset are used to quantify the impact of these measured time-domain errors on the pressure profile. This analysis shows that the SMER is raised by more than 6 dB and the beam is offset by more than 1 mm from its programmed focal position. This calibration methodology is then demonstrated using a steel non-destructive testing (NDT) sample with three side-drilled holes (SDHs). The time delay errors from transmission and reception are introduced into the time-of-flight (TOF) calculation for each ray path in the TFM. This results in an enhancement in the accuracy of defect localisation in the TFM image.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

Estimating interannual variability arising from weather events

2001 ◽  
Vol 38 (A) ◽  
pp. 274-288 ◽  
Author(s):  
Xiaogu Zheng ◽  
James Renwick
Keyword(s):  
Frequency Domain ◽  
Interannual Variability ◽  
Time Domain ◽  
Synthetic Data ◽  
Estimation Procedure ◽  
Frequency Domain Method ◽  
Domain Method ◽  
Weather Events ◽  
Long Time ◽  
The Time Domain

The advantages and limitations of frequency domain and time domain methods for estimating the interannual variability arising from day-to-day weather events are summarized. A modification of the time domain method is developed and its application in examining a precondition for the frequency domain method is demonstrated. A combined estimation procedure is proposed: it takes advantage of the strengths of both methods. The estimation procedures are tested with sets of synthetic data and are applied to long time series of three meteorological parameters. The impacts of the different methods on tests of potential long-range predictability for seasonal means are also discussed.

Time Domain Fatigue Life Analysis of Offshore Jacket Structure

2019 ◽  
Author(s):  
Yan Wei Wu
Keyword(s):  
Fatigue Life ◽  
Fatigue Damage ◽  
Time Domain ◽  
Offshore Wind ◽  
Support Structure ◽  
Structural Fatigue ◽  
Long Time ◽  
Fatigue Life Analysis ◽  
Stress Concentration Factors ◽  
The Time Domain

Abstract Offshore wind system encountered wind, wave, current, soil, and other environmental loads. The support structure is randomly loaded for a long time, which is more likely to cause fatigue damage. In this paper, the NREL 5MW wind turbine and OC4 jacket support structure is selected to perform the time domain fatigue analysis. Commercial software Bladed and SACS are used to perform the required structural responses and fatigue strength calculations. The Stress Concentration Factors (SCF) and S-N curves for the stress calculations of tubular joints are adopted based on the recommendation of DNV GL guidelines. The magnitude of the stress variation range and the corresponding number of counts are obtained by using the rain-flow counting algorithm. Finally, the Palmgren-Miner’s rule is adopted to calculate the cumulative damage ratio and the fatigue life can then be estimated. Fatigue damage ratio and structural fatigue life of each joint during 20 years of operation period are evaluated.

scholarly journals DIGITAL CONTROLLED OSCILLATOR (DCO) FOR ALL DIGITAL PHASE-LOCKED LOOP (ADPLL) – A REVIEW

2019 ◽  
Vol 82 (1) ◽  
Author(s):  
Florence Choong ◽  
Mamun Ibne Reaz ◽  
Mohamad Ibrahim Kamaruzzaman ◽  
Md. Torikul Islam Badal ◽  
Araf Farayez ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Process Technology ◽  
Chip Area ◽  
Digital Phase ◽  
Low Power Dissipation

Digital controlled oscillator (DCO) is becoming an attractive replacement over the voltage control oscillator (VCO) with the advances of digital intensive research on all-digital phase locked-loop (ADPLL) in complementary metal-oxide semiconductor (CMOS) process technology. This paper presents a review of various CMOS DCO schemes implemented in ADPLL and relationship between the DCO parameters with ADPLL performance. The DCO architecture evaluated through its power consumption, speed, chip area, frequency range, supply voltage, portability and resolution. It can be concluded that even though there are various schemes of DCO that have been implemented for ADPLL, the selection of the DCO is frequently based on the ADPLL applications and the complexity of the scheme. The demand for the low power dissipation and high resolution DCO in CMOS technology shall remain a challenging and active area of research for years to come. Thus, this review shall work as a guideline for the researchers who wish to work on all digital PLL.

scholarly journals Design and Simulation Study of Active Baluns Circuits for WiMAX Applications

2019 ◽  
Vol 7 (1) ◽  
Author(s):  
Frederick Ray I. Gomez ◽  
John Richard E. Hizon ◽  
Maria Theresa G. De Leon
Keyword(s):  
Phase Difference ◽  
Simulation Study ◽  
Noise Figure ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Common Source ◽  
Cmos Process ◽  
Common Gate ◽  
Active Balun

The paper presents a design and simulation study of three active balun circuits implemented in a standard 90nm Complementary Metal-Oxide Semiconductor (CMOS) process namely: (1) common-source/drain active balun; (2) common-gate with common-source active balun; and (3) differential active balun.  The active balun designs are intended for Worldwide Interoperability for Microwave Access (WiMAX) applications operating at frequency 5.8GHz and with supply voltage of 1V.  Measurements are taken for parameters such as gain difference, phase difference, and noise figure.  All designs achieved gain difference of less than 0.23dB, phase difference of 180° ± 7.1°, and noise figure of 7.2–9.85dB, which are comparable to previous designs and researches.  Low power consumption attained at the most 4.45mW.

scholarly journals Experimental demonstration of high-gain CMOS inverter operation at low Vdd down to 0.5 V consisting of WSe2 n/p FETs

2021 ◽  
Author(s):  
Takamasa KAWANAGO ◽  
Takahiro Matsuzaki ◽  
Ryosuke Kajikawa ◽  
Iriya Muneta ◽  
Takuya HOSHII ◽  
...  
Keyword(s):  
Gate Dielectric ◽  
Supply Voltage ◽  
Transition Metal Dichalcogenides ◽  
High Gain ◽  
Oxide Semiconductor ◽  
Poly Vinyl Alcohol ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Power Supply Voltage ◽  
Doping Technique

Abstract In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (Vdd), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer (SAM)/aluminum oxide (AlOx) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at Vdd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides (TMDC)-based devices and circuits.

A New Technique for Designing Low-Power High-Speed Domino Logic Circuits in FinFET Technology

2019 ◽  
Vol 28 (10) ◽  
pp. 1950165 ◽  
Author(s):  
Sandeep Garg ◽  
Tarun K. Gupta
Keyword(s):  
Low Power ◽  
High Speed ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Power Reduction ◽  
Maximum Power ◽  
Oxide Semiconductor ◽  
Domino Logic ◽  
Maximum Delay

In this paper, a fin field-effect transistor (FinFET)-based domino technique dynamic node-driven feedback transistor domino logic (DNDFTDL) is designed for low-power, high-speed and improved noise performance. In the proposed domino technique, the concept of current division is explored below the evaluation network for enhancement of performance parameters. Simulations are carried out for 32-nm complementary metal–oxide–semiconductor (CMOS) and FinFET node using HSPICE for 2-, 4-, 8- and 16-input OR gates with a DC supply voltage of 0.9[Formula: see text]V. Proposed technique shows a maximum power reduction of 73.93% in FinFET short-gate (SG) mode as compared to conditional stacked keeper domino logic (CSKDL) technique and a maximum power reduction of 72.12% as compared to modified high-speed clocked delay domino logic (M-HSCD) technique in FinFET low-power (LP) mode. The proposed technique shows a maximum delay reduction of 35.52% as compared to voltage comparison domino (VCD) technique in SG mode and a reduction of 25.01% as compared to current mirror footed domino logic (CMFD) technique in LP mode. The unity noise gain (UNG) of the proposed circuit is 1.72–[Formula: see text] higher compared to different existing techniques in FinFET SG mode and is 1.42–[Formula: see text] higher in FinFET LP mode. The Figure of Merit (FOM) of the proposed circuit is up to [Formula: see text] higher as compared to existing domino logic techniques because of lower values of power, delay and area and higher values of UNG of the proposed circuit. In addition, the proposed technique shows a maximum power reduction of up to 68.64% in FinFET technology as compared to its counterpart in CMOS technology.

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