scholarly journals A High-Speed Low-Cost VLSI System Capable of On-Chip Online Learning for Dynamic Vision Sensor Data Classification

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4715
Author(s):  
Wei He ◽  
Jinguo Huang ◽  
Tengxiao Wang ◽  
Yingcheng Lin ◽  
Junxian He ◽  
...  
Keyword(s):  
Online Learning ◽  
High Speed ◽  
Low Cost ◽  
High Energy ◽  
Training Procedure ◽  
Vision Sensor ◽  
Clock Frequency ◽  
Dynamic Vision ◽  
Vlsi System ◽  
On Chip

This paper proposes a high-speed low-cost VLSI system capable of on-chip online learning for classifying address-event representation (AER) streams from dynamic vision sensor (DVS) retina chips. The proposed system executes a lightweight statistic algorithm based on simple binary features extracted from AER streams and a Random Ferns classifier to classify these features. The proposed system’s characteristics of multi-level pipelines and parallel processing circuits achieves a high throughput up to 1 spike event per clock cycle for AER data processing. Thanks to the nature of the lightweight algorithm, our hardware system is realized in a low-cost memory-centric paradigm. In addition, the system is capable of on-chip online learning to flexibly adapt to different in-situ application scenarios. The extra overheads for on-chip learning in terms of time and resource consumption are quite low, as the training procedure of the Random Ferns is quite simple, requiring few auxiliary learning circuits. An FPGA prototype of the proposed VLSI system was implemented with 9.5~96.7% memory consumption and <11% computational and logic resources on a Xilinx Zynq-7045 chip platform. It was running at a clock frequency of 100 MHz and achieved a peak processing throughput up to 100 Meps (Mega events per second), with an estimated power consumption of 690 mW leading to a high energy efficiency of 145 Meps/W or 145 event/μJ. We tested the prototype system on MNIST-DVS, Poker-DVS, and Posture-DVS datasets, and obtained classification accuracies of 77.9%, 99.4% and 99.3%, respectively. Compared to prior works, our VLSI system achieves higher processing speeds, higher computing efficiency, comparable accuracy, and lower resource costs.

A High Speed 8B/10B Encoder/Decoder Design Based on Low Cost FPGA

2012 ◽  
Vol 462 ◽  
pp. 361-367 ◽  
Author(s):  
Zhang Jin Chen ◽  
Guo Hai Zhong ◽  
Zhuo Bi
Keyword(s):  
High Speed ◽  
Single Channel ◽  
Low Cost ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Parallel Pipeline ◽  
Quartus Ii ◽  
Simulation Results ◽  
Decoder Design ◽  
Timing Simulation

A high speed 8B/10B Encoder/Decoder is presented in this paper. The Encoder/Decoder is based on Altera’s low cost FPGA Cyclone family. The Encoder/Decoder includes parallel pipeline structure. The Encoder/Decoder is applied to the Serializer/Deserializer (SERDES) of high-speed serial bus. The Encoder/Decoder is synthesized and simulated by Quartus II 9.1. The synthesis and analysis results show the maximum frequency is more than 359MHz. The timing simulation results show the clock frequency is more than 125 MHz. The single channel data rate of serial bus can get to 1.25Gbps. The proposed Encoder/Decoder can meet the requirements of most high-speed serial bus.

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

SENSING AND ACTUATING BIO-MATERIALS ON STANDARD CMOS SUBSTRATES

2013 ◽  
Vol 22 (02) ◽  
pp. 1250081 ◽  
Author(s):  
FAISAL T. ABU-NIMEH ◽  
FATHI M. SALEM
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Low Cost ◽  
Magnetic Bead ◽  
Column Switching ◽  
Parallel Operation ◽  
Coil Array ◽  
Lab On Chip ◽  
On Chip ◽  
Array Sensing

We present a low-cost, low-power, high efficiency, and portable integrated implementations of a lab-on-chip for magnetic molecular level sensing manipulation, and diagnosis. The design features an all-integrated programmable magnetic coil array for sensing and actuating small magnetic bead objects. The coil array is selectively and dynamically controlled using the smallest permissible vertical coil inductors in this technology. Each cell, composed of the coil and its logical control circuitry, can detect small objects in the order of 1 μm diameter as well as emit eight programmable magnetic field levels for manipulation. All array sensing and driving components are shared to reduce the overall imprint. They are tuned towards the 900 s MHz ISM band and incorporating high-speed serial row/column switching up to 40 MHz for seamless pseudo-parallel operation.

A modified Fresnel-based algorithm for 3D microwave imaging of metal objects

2018 ◽  
Vol 11 (4) ◽  
pp. 313-325
Author(s):  
Farshad Zamiri ◽  
Abdolreza Nabavi
Keyword(s):  
High Speed ◽  
Fourier Transforms ◽  
Low Cost ◽  
Three Dimensional ◽  
Computation Time ◽  
Microwave Imaging ◽  
Reconstruction Algorithms ◽  
Clock Frequency ◽  
Pipeline Architecture ◽  
The Impact

AbstractMicrowave holography technique reconstructs a target image using recorded amplitudes and phases of the signals reflected from the target with Fast Fourier Transform (FFT)-based algorithms. The reconstruction algorithms have two or more steps of two- and three-dimensional Fourier transforms, which have a high computational load. In this paper, by neglecting the impact of target depth on image reconstruction, an efficient Fresnel-based algorithm is proposed, involving only one-step FFT for both single- and multi-frequency microwave imaging. Numerous tests have been performed to show the effectiveness of the proposed algorithm including planar and non-planar targets, using the raw data gathered by means of a scanner operating in X-band. Finally, a low-cost and high-speed hardware architecture based on fixed-point arithmetic is introduced which reconstructs the planar targets. This pipeline architecture was tested on field programmable gate arrays operating at 200 MHz clock frequency, which illustrates more than 30 times improvement in computation time compared with a computer.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Toward high-speed, low-cost, on-chip silicon optical interconnects

SPIE Newsroom ◽  
2011 ◽  
Author(s):  
Xi Xiao ◽  
Haihua Xu ◽  
Yingtao Hu ◽  
Zhiyong Li ◽  
Yude Yu ◽  
...  
Keyword(s):  
Optical Interconnects ◽  
High Speed ◽  
Low Cost ◽  
On Chip

Design of a SoC With High-Speed DDC for Software Radio Receiver

2012 ◽  
Vol 605-607 ◽  
pp. 1875-1879 ◽  
Author(s):  
Jun Deng ◽  
Lin Tao Liu ◽  
Yu Jing Li ◽  
Xiao Zong Huang ◽  
Xu Huang ◽  
...  
Keyword(s):  
High Speed ◽  
Software Radio ◽  
Intermediate Frequency ◽  
Cmos Technology ◽  
Radio Receiver ◽  
Clock Frequency ◽  
Baseband Signal ◽  
Baseband Signal Processing ◽  
Good Potential ◽  
On Chip

This paper presents a novel scheme for software radio receiver application, which integrates a high-speed digital down converter (DDC) block into a SoC (system on chip) based on OR1200 CPU. The proposed design can transform intermediate frequency (IF) signal to baseband signal and realize the real-time baseband signal processing. The simulation results indicate that the design is capable of accepting data at a 200MHz sample rate and the verification results based on Xilinx FPGA show that the SFDR of DDC can reach to 70.59dBFS.The synthesized results on 0.18um CMOS technology reveal that the maximum clock frequency can reach to 116MHz and the total area is 5.662mm2, and the corresponding power consumption is below 150mW. It should have a good potential for wireless communication applications.

scholarly journals Dynamic Vision Sensor integration on FPGA-based CNN accelerators for high-speed visual classification

2021 ◽  
Author(s):  
Alejandro Linares-Barranco ◽  
Antonio Rios-Navarro ◽  
Salvador Canas-Moreno ◽  
Enrique Piñero-Fuentes ◽  
Ricardo Tapiador-Morales ◽  
...  
Keyword(s):  
High Speed ◽  
Sensor Integration ◽  
Vision Sensor ◽  
Visual Classification ◽  
Dynamic Vision
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