scholarly journals Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems

Sensors ◽  
2020 ◽  
Vol 20 (8) ◽  
pp. 2430 ◽  
Author(s):  
Kiho Seong ◽  
Dong-Kyu Jung ◽  
Dong-Hyun Yoon ◽  
Jae-Soub Han ◽  
Ju-Eon Kim ◽  
...  

Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converters (ADCs) continues to grow. The successive approximation register (SAR) ADCs are the most powerful candidate to meet these demands, attracting both industries and academia. In particular, recent time-interleaved SAR ADCs show that multi-giga sample per second (GS/s) can be achieved by overcoming the challenges of high-speed implementation of existing SAR ADCs. However, there are still critical issues that need to be addressed before the time-interleaved SAR ADCs can be applied in real commercial applications. The most well-known problem is that the time-interleaved SAR ADC architecture requires multiple sub-ADCs, and the mismatches between these sub-ADCs can significantly degrade overall ADC performance. And one of the most difficult mismatches to solve is the sampling timing skew. Recently, research to solve this timing-skew problem has been intensively studied. In this paper, we focus on the cutting-edge timing-skew calibration technique using a window detector. Based on the pros and cons analysis of the existing techniques, we come up with an idea that increases the benefits of the window detector-based timing-skew calibration techniques and minimizes the power and area overheads. Finally, through the continuous development of this idea, we propose a timing-skew calibration technique using a comparator offset-based window detector. To demonstrate the effectiveness of the proposed technique, intensive works were performed, including the design of a 7-bit, 2.5 GS/s 5-channel time-interleaved SAR ADC and various simulations, and the results prove excellent efficacy of signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 40.79 dB and 48.97 dB at Nyquist frequency, respectively, while the proposed window detector occupies only 6.5% of the total active area, and consumes 11% of the total power.

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 73
Author(s):  
Van-Thanh Ta ◽  
Van-Phuc Hoang ◽  
Van-Phu Pham ◽  
Cong-Kha Pham

The time-interleaved analog-to-digital converters (TIADCs), performance is seriously affected by channel mismatches, especially for the applications in the next-generation communication systems. This work presents an improved all-digital background calibration technique for TIADCs by combining the Hadamard transform for calibrating gain and timing mismatches and averaging for offset mismatch cancellation. The numerical simulation results show that the proposed calibration technique completely suppresses the spurious images due to the channel mismatches at the output spectrum, which increases the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) by 74 dB and 43.7 dB, respectively. Furthermore, the hardware co-simulation on the field programmable gate array (FPGA) platform is performed to confirm the effectiveness of the proposed calibration technique. The simulation and experimental results clarify the improvement of the proposed calibration technique in the TIADC’s performance.


Author(s):  
Wenning Jiang ◽  
Yan Zhu ◽  
Chi-Hang Chan ◽  
Boris Murmann ◽  
Rui Paulo Martins
Keyword(s):  
Sar Adc ◽  

2019 ◽  
Vol 66 (2) ◽  
pp. 489-501
Author(s):  
Dezhi Xing ◽  
Yan Zhu ◽  
Chi-Hang Chan ◽  
Franco Maloberti ◽  
Seng-Pan U ◽  
...  

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 305 ◽  
Author(s):  
Dong Wang ◽  
Xiaoge Zhu ◽  
Xuan Guo ◽  
Jian Luan ◽  
Lei Zhou ◽  
...  

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.


2016 ◽  
Vol 16 (3) ◽  
pp. 274-286
Author(s):  
Sunghun Cho ◽  
DongSoo Lee ◽  
Juri Lee ◽  
Hyung-Gu Park ◽  
YoungGun Pu ◽  
...  
Keyword(s):  
Sar Adc ◽  

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