scholarly journals Harmonic Distortion Optimization for Sigma-Delta Modulators Interface Circuit of TMR Sensors

Sensors ◽  
2020 ◽  
Vol 20 (4) ◽  
pp. 1041
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Harmonic Distortion ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Signal Spectrum ◽  
Magnetic Multilayer ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Front End

The tunneling magnetoresistance micro-sensors (TMR) developed by magnetic multilayer material has many advantages, such as high sensitivity, high frequency response, and good reliability. It is widely used in military and civil fields. This work presents a high-performance interface circuit for TMR sensors. Because of the nonlinearity of signal conversion between sensitive structure and interface circuit in feedback loop and forward path, large harmonic distortion occurs in output signal spectrum, which greatly leads to the reduction of SNDR (signal noise distortion rate). In this paper, we analyzed the main source of harmonic distortion in closed-loop detection circuit and establish an accurate harmonic distortion model in TMR micro-sensors system. Some factors are considered, including non-linear gain of operational amplifier unit, effective gain bandwidth, conversion speed, nonlinearity of analog transmission gate, and nonlinearity of polycrystalline capacitance in high-order sigma-delta system. We optimized the CMOS switch and first-stage integrator in the switched-capacitor circuit. The harmonic distortion parameter is optimally designed in the TMR sensors system, aiming at the mismatch of misalignment of front-end system, non-linearity of quantizer, non-linearity of capacitor, and non-linearity of analog switch. The digital output is attained by the interface circuit based on a low-noise front-end interface circuit and a third-order sigma-delta modulator. The digital interface circuit is implemented by 0.35μm CMOS (complementary metal oxide semiconductor) technology. The high-performance digital TMR sensors system is implemented by double chip integration and the active interface circuit area is about 3.2 × 2 mm. The TMR sensors system consumes 20 mW at a single 5 V supply voltage. The TMR sensors system can achieve a linearity of 0.3% at full scale range (±105 nT) and a resolution of 0.25 nT/Hz1/2(@1Hz).

scholarly journals A High-Performance Digital Interface Circuit for a High-Q Micro-Electromechanical System Accelerometer

Micromachines ◽  
2018 ◽  
Vol 9 (12) ◽  
pp. 675 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Performance ◽  
Low Noise ◽  
Electromechanical System ◽  
Digital Interface ◽  
Interface Circuit ◽  
Mems Accelerometer ◽  
High Q ◽  
Front End ◽  
Micro Electromechanical System ◽  
Micro Accelerometer

Micro-electromechanical system (MEMS) accelerometers are widely used in the inertial navigation and nanosatellites field. A high-performance digital interface circuit for a high-Q MEMS micro-accelerometer is presented in this work. The mechanical noise of the MEMS accelerometer is decreased by the application of a vacuum-packaged sensitive element. The quantization noise in the baseband of the interface circuit is greatly suppressed by a 4th-order loop shaping. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a 4th-order Sigma-Delta (ΣΔ) modulator. The stability of high-order ΣΔ was studied by the root locus method. The gain of the integrators was reduced by using the proportional scaling technique. The low-noise front-end detection circuit was proposed with the correlated double sampling (CDS) technique to eliminate the 1/f noise and offset. The digital interface circuit was implemented by 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. The high-performance digital accelerometer system was implemented by double chip integration and the active interface circuit area was about 3.3 mm × 3.5 mm. The high-Q MEMS accelerometer system consumed 10 mW from a single 5 V supply at a sampling frequency of 250 kHz. The micro-accelerometer system could achieve a third harmonic distortion of −98 dB and an average noise floor in low-frequency range of less than −140 dBV; a resolution of 0.48 μg/Hz1/2 (@300 Hz); a bias stability of 18 μg by the Allen variance program in MATLAB.

Design of High-SNR CMOS Interface Circuit for Micro-Machined Gyroscope

2011 ◽  
Vol 483 ◽  
pp. 508-512
Author(s):  
Hai Xi Lu ◽  
Yong Ping Xu ◽  
Shou Rong Wang
Keyword(s):  
High Gain ◽  
Low Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Interface Circuit ◽  
Fully Differential ◽  
Chopper Stabilization ◽  
Front End ◽  
Cascade Structure ◽  
Stabilization Technique

A CMOS integrated interface circuit for micro-machined gyroscope containing a novel front-end and 6th-order Sigma-delta modulator is presented in this paper. To reduce the noise coming from the sensor and circuit, the front-end is accomplished by a switched-capacitor architecture, which constructed by a high-gain fully-differential amplifier and improved by chopper-stabilization technique, and work under a designed charging and sampling logic scheme. A cascade 6th-order Sigma-Delta modulator is designed to get high resolution, reduce quantized error and suppress the instability brought by high-order modulator. With the cascade structure and 16-bit resolution 32 OSR, the modulator outputs 3-bits digital stream. The whole circuit is designed with AMS technique and 3.3V power consumption. The simulation result presents that the interface circuit performs a appointed under a low-noise design specification in signal band, and the SNR of the circuit achieves remarkable value of 106dB.

scholarly journals A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

2016 ◽  
Vol 13 (13) ◽  
pp. 20160457-20160457
Author(s):  
Xinpeng Di ◽  
Weiping Chen ◽  
Xiaowei Liu ◽  
Liang Yin ◽  
Qiang Fu
Keyword(s):  
High Performance ◽  
Harmonic Distortion ◽  
Sigma Delta ◽  
Interface Circuit

scholarly journals A 1.5–40 GHz frequency modulated continuous wave radar receiver front-end

2021 ◽  
pp. 1-11
Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger
Keyword(s):  
Continuous Wave ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Ultra Wideband ◽  
Front End ◽  
Wave Radar ◽  
Bicmos Technology ◽  
Circuit Components ◽  
High Band

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

Study on Performance Analysis of CMOS RF front-end circuits for 2.4GHz Wireless Applications

2012 ◽  
pp. 68-73
Author(s):  
M. Sumathi ◽  
S. Malarvizhi
Keyword(s):  
Performance Analysis ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Low Noise ◽  
Design System ◽  
Wireless Applications ◽  
Front End ◽  
Trade Offs ◽  
Front End Circuits

In this paper, low voltage design concepts and new CMOS front-end circuits for 2.4GHz wireless applications are presented. The performances of these circuits are analysed and compared with other existing structures using TSMC 0.18-μm CMOS technology scale. The design trade-offs between impedance matching, power gain and noise figure of low-noise amplifiers are highlighted. The advantage of the introduced mixer topology is expressed in terms of conversion gain, noise figure and linearity. At a supply voltage of 1.8V, the design and performance analysis have been performed using Agilent’s Advanced Design System (ADS2009) software.

scholarly journals A Fully Integrated 64-Channel Recording System for Extracellular Raw Neural Signals

Electronics ◽  
2021 ◽  
Vol 10 (21) ◽  
pp. 2726
Author(s):  
Xiangwei Zhang ◽  
Quan Li ◽  
Chengying Chen ◽  
Yan Li ◽  
Fuqiang Zuo ◽  
...  
Keyword(s):  
Harmonic Distortion ◽  
Field Potential ◽  
Low Noise ◽  
Recording System ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Cmos Process ◽  
Neural Signals ◽  
Fully Integrated ◽  
Rail To Rail

This paper presents a fully integrated 64-channel neural recording system for local field potential and action potential. It mainly includes 64 low-noise amplifiers, 64 programmable amplifiers and filters, 9 switched-capacitor (SC) amplifiers, and a 10-bit successive approximation register analogue-to-digital converter (SAR ADC). Two innovations have been proposed. First, a two-stage amplifier with high-gain, rail-to-rail input and output, and dynamic current enhancement improves the speed of SC amplifiers. The second is a clock logic that can be used to align the switching clock of 64 channels with the sampling clock of ADC. Implemented in an SMIC 0.18 μm Complementary Metal Oxide Semiconductor (CMOS) process, the 64-channel system chip has a die area of 4 × 4 mm2 and is packaged in a QFN−88 of 10 × 10 mm2. Supplied by 1.8 V, the total power is about 8.28 mW. For each channel, rail-to-rail electrode DC offset can be rejected, the referred-to-input noise within 1 Hz–10 kHz is about 5.5 μVrms, the common-mode rejection ratio at 50 Hz is about 69 dB, and the output total harmonic distortion is 0.53%. Measurement results also show that multiple neural signals are able to be simultaneously recorded.

scholarly journals A Wideband Noise and Harmonic Distortion Canceling Low-Noise Amplifier for High-Frequency Ultrasound Transducers

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8476
Author(s):  
Yuxuan Tang ◽  
Yulang Feng ◽  
He Hu ◽  
Cheng Fang ◽  
Hao Deng ◽  
...  
Keyword(s):  
High Frequency ◽  
Harmonic Distortion ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Cmos Process ◽  
Ultrasound Transducers ◽  
High Frequency Ultrasound ◽  
Front End ◽  
Noise Amplifier ◽  
Frequency Ultrasound

This paper presents a wideband low-noise amplifier (LNA) front-end with noise and distortion cancellation for high-frequency ultrasound transducers. The LNA employs a resistive shunt-feedback structure with a feedforward noise-canceling technique to accomplish both wideband impedance matching and low noise performance. A complementary CMOS topology was also developed to cancel out the second-order harmonic distortion and enhance the amplifier linearity. A high-frequency ultrasound (HFUS) and photoacoustic (PA) imaging front-end, including the proposed LNA and a variable gain amplifier (VGA), was designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt (Hz), an input return loss (S11) of better than −16 dB, a voltage gain of 37 dB, and a total harmonic distortion (THD) of −55 dBc while dissipating a power of 37 mW, leading to a noise efficiency factor (NEF) of 2.66.

Study of a closed-loop high-precision front-end circuit for tunneling magneto-resistance sensors

2019 ◽  
Vol 33 (08) ◽  
pp. 1950085 ◽  
Author(s):  
Xiangyu Li ◽  
Jianping Hu ◽  
Xiaowei Liu
Keyword(s):  
High Precision ◽  
Closed Loop ◽  
Low Frequency ◽  
Cmos Technology ◽  
Low Noise ◽  
Corner Frequency ◽  
Cmos Process ◽  
Interface Circuit ◽  
Front End ◽  
Magneto Resistance

A closed-loop high-precision front-end interface circuit in a standard 0.35 [Formula: see text]m CMOS technology for a tunneling magneto-resistance (TMR) sensor is presented in this paper. In consideration of processing a low frequency and weak geomagnetic signal, a low-noise front-end detection circuit is proposed with chopper technique to eliminate the 1/f noise and offset of operational amplifier. A novel ripple suppression loop is proposed for eliminating the ripple in a tunneling magneto-resistance sensor interface circuit. Even harmonics is eliminated by fully differential structure. The interface is fabricated in a standard 0.35 [Formula: see text]m CMOS process and the active circuit area is about [Formula: see text]. The interface chip consumes 7 mW at a 5 V supply and the 1/f noise corner frequency is lower than 1 Hz. The interface circuit of TMR sensors can achieve a better noise level of [Formula: see text]. The ripple can be suppressed to less than 10 [Formula: see text]V by ripple suppression loop.

scholarly journals CMOS Low-Dropout Voltage Regulator Design Trends: An Overview

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 193
Author(s):  
Mohammad Arif Sobhan Bhuiyan ◽  
Md. Rownak Hossain ◽  
Khairun Nisa’ Minhad ◽  
Fahmida Haque ◽  
Mohammad Shahriar Khan Hemel ◽  
...  
Keyword(s):  
High Performance ◽  
Supply Voltage ◽  
Process Variations ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Oxide Semiconductor ◽  
Voltage Regulator ◽  
Stable Operation ◽  
Short Channel ◽  
Voltage Range

Systems-on-Chip’s (SoC) design complexity demands a high-performance linear regulator architecture to maintain a stable operation for the efficient power management of today’s devices. Over the decades, the low-dropout (LDO) voltage regulator design has gained attention due to its design scalability with better performance in various application domains. Industry professionals as well as academia have put forward their innovations such as event-driven explicit time-coding, exponential-ratio array, switched RC bandgap reference circuit, etc., to make a trade-off between several performance parameters such as die area, ripple rejection, supply voltage range, and current efficiency. However, current LDO architectures in micro and nanometer complementary metal–oxide–semiconductor (CMOS) technology face some challenges, such as short channel effects, gate leakage, fabrication difficulty, and sensitivity to process variations at nanoscale. This review presents the LDO architectures, optimization techniques, and performance comparisons in different LDO design domains such as digital, analog, and hybrid. In this review, various state-of-the-art circuit topologies, deployed for the betterment of LDO performance and focusing on the specific parameter up-gradation to the overall improvement of the functionality, are framed, which will serve as a comparative study and reference for researchers.

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