scholarly journals A Straightforward Approach for Synthesizing Electromechanical Sigma-Delta MEMS Accelerometers

Sensors ◽  
2019 ◽  
Vol 20 (1) ◽  
pp. 91 ◽  
Author(s):  
Dongliang Chen ◽  
Liang Yin ◽  
Qiang Fu ◽  
Wenbo Zhang ◽  
Yihang Wang ◽  
...  

The EM- Σ Δ (electromechanical sigma-delta) approach is a concise and efficient way to realize the digital interface for micro-electromechanical systems (MEMS) accelerometers. However, including a fixed MEMS element makes the synthesizing of the EM- Σ Δ loop an intricate problem. The loop parameters of EM- Σ Δ can not be directly mapped from existing electrical Σ Δ modulator, and the synthesizing problem relies an experience-dependent trail-and-error procedure. In this paper, we provide a new point of view to consider the EM- Σ Δ loop. The EM- Σ Δ loop is analyzed in detail from aspects of the signal loop, displacement modulation path and digital quantization loop. By taking a separate consideration of the signal loop and quantization noise loop, the design strategy is made clear and straightforward. On this basis, a discrete-time PID (proportional integral differential) loop compensator is introduced which enhances the in-band loop gain and suppresses the displacement modulation path, and hence, achieves better performance in system linearity and stability. A fifth-order EM- Σ Δ accelerometer system was designed and fabricated using 0.35 μ m CMOS-BCD technology. Based on proposed architecture and synthesizing procedure, the design effort was saved, and the in-band performance, linearity and stability were improved. A noise floor of 1 μ g / Hz , with a bandwidth 1 kHz and a dynamic range of 140 dB was achieved.

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.


2013 ◽  
Vol 562-565 ◽  
pp. 380-386
Author(s):  
Xiao Wei Liu ◽  
Hong Lin Xu ◽  
Bing Jun Lv ◽  
Jia Jun Zhou ◽  
Song Chen ◽  
...  

A high-order interface circuit based on sigma-delta (ΣΔ) modulation is advantageous to enhance the resolution and reduce the quantization noise of micro-accelerometer, while the performance is restricted by the effect of nonlinearity of op-amp, electrostatic force feedback and quantizer. A fifth-order closed-loop ΣΔ capacitive accelerometer is proposed in this paper and a theoretic nonlinearity of the accelerometer was investigated. The nonlinear behavioral models based on SIMULINK are given in the paper. The simulation and test result are presented through optimization based on the nonlinearity analysis at last.


2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.


1998 ◽  
Vol 167 ◽  
pp. 163-170
Author(s):  
Yutaka Uchida

AbstractWe describe in this paper some of the findings of the Yohkoh satellite about the coronal structure surrounding dark filaments in the pre-event and initial phases of high latitude arcade formation events. The knowledge of pre-event structure and its change is essential for the proper understanding of the arcade flaring process from the causality point of view. The wide dynamic range and high sensitivity obervations by Yohkoh allow us to look into the faint structures and their changes with the use of a faint-feature-enhancing technique in the image analysis.


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