scholarly journals Power Efficient Random Access for Massive NB-IoT Connectivity

Sensors ◽  
2019 ◽  
Vol 19 (22) ◽  
pp. 4944 ◽  
Author(s):  
Mamta Agiwal ◽  
Mukesh Kumar Maheshwari ◽  
Hu Jin

Sensors enabled Internet of things (IoT) has become an integral part of the modern, digital and connected ecosystem. Narrowband IoT (NB-IoT) technology is one of its economical versions preferable when low power and resource limited sensors based applications are considered. One of the major characteristics of NB-IoT technology is its offer of reliable coverage enhancement (CE) which is achieved by repeating the transmission of signals. This repeated transmission of the same signal challenges power saving in low complexity NB-IoT devices. Additionally, the NB-IoT devices are expected to suffer from congestion due to simultaneous random access procedures (RAPs) from an enormous number of devices. Multiple RAP reattempts would further reduce the power saving in NB-IoT devices. We propose a novel power efficient RAP (PE-RAP) for reducing power consumption of NB-IoT devices in a highly congested environment. The existing RAP do not differentiate the failures due to poor channel conditions or due to collision. After the RAP failure either due to collision or poor channel, the devices can apply power ramping or can transit to a higher CE level with higher repetition configuration. In the proposed PE-RAP, the NB-IoT devices can re-ascertain the channel conditions after an RAP attempt failure such that the impediments due to poor channel are reduced. The power increments and repetition enhancements are applied only when necessary. We probabilistically obtain the chances of RAP reattempts. Subsequently, we evaluate the average power consumption by devices in different CE levels for different repetition configurations. We validate our analysis by simulation studies.

2013 ◽  
Vol 22 (03) ◽  
pp. 1350001 ◽  
Author(s):  
YOONJIN KIM

Coarse-grained reconfigurable architectures (CGRA) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of IP cores. Reducing power in configuration cache is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, I propose a power-efficient configuration cache structure based on two design schemes — one is a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration and another is a dynamic context management strategy for power saving in configuration cache. This power-efficient approach works without degrading the performance and flexibility of CGRA. Experimental results show that the proposed approach saves 56.50%/86.84% of the average power in write/read-operation of configuration cache compared to the previous design.


Author(s):  
Alekhya Orugonda ◽  
V. Kiran Kumar

Background: It is important to minimize bandwidth that improves battery life, system reliability and other environmental concerns and energy optimization.It also do everything within their power to reduce the amount of data that flows through their pipes.To increase resource exertion, task consolidation is an effective technique, greatly enabled by virtualization technologies, which facilitate the concurrent execution of several tasks and, in turn, reduce energy consumption. : MaxUtil, which aims to maximize resource exertion, and Energy Conscious Task Consolidation which explicitly takes into account both active and idle energy consumption. Method: In this paper an Energy Aware Cloud Load Balancing Technique (EACLBT) is proposed for the performance improvement in terms of energy and run time. It predicts load of host after VM allocation and if according to prediction host become overloaded than VM will be created on different host. So it minimize the number of migrations due to host overloading conditions. This proposed technique results in minimize bandwidth and energy utilization. Results: The result shows that the energy efficient method has been proposed for monitor energy exhaustion and support static and dynamic system level optimization.The EACLBT can reduce the number of power-on physical machine and average power consumption compare to other deploy algorithms with power saving.Besides minimization in bandwidth along with energy exertion, reduction in the number of executed instructions is also achieved. Conclusion: This paper comprehensively describes the EACLBT (Energy Aware Cloud Load Balancing Technique) to deploy the virtual machines for power saving purpose. The average power consumption is used as performance metrics and the result of PALB is used as baseline. The EACLBT can reduce the number of power-on physical machine and average power consumption compare to other deploy algorithms with power saving. It shown that on average an idle server consumes approximately 70% of the power consumed by the server running at the full CPU speed.The performance holds better for Common sub utterance elimination. So, we can say the proposed Energy Aware Cloud Load Balancing Technique (EACLBT) is effective in bandwidth minimization and reduction of energy exertion.


Energies ◽  
2020 ◽  
Vol 13 (22) ◽  
pp. 5875
Author(s):  
Yuan Ren ◽  
Xuewei Zhang ◽  
Guangyue Lu

With the tremendous increase of heterogeneous Internet of Things (IoT) devices and the different service requirements of these IoT applications, machine-type communication (MTC) has attracted considerable attention from both industry and academia. Owing to the prominent advantages of supporting pervasive connectivity and wide area coverage, the cellular network is advocated as the potential wireless solution to realize IoT deployment for MTC, and this creative network paradigm is called the cellular IoT (C-IoT). In this paper, we propose the three-layer structured C-IoT architecture for MTC and review the challenges for deploying green C-IoT. Then, effective strategies for realizing green C-IoT are presented, including the energy efficient and energy harvesting schemes. We put forward several strategies to make the C-IoT run in an energy-saving manner, such as efficient random access and barring mechanisms, self-adapting machine learning predictions, scheduling optimization, resource allocation, fog computing, and group-oriented transmission. As for the energy harvesting schemes, the ambient and dedicated energy harvesting strategies are investigated. Afterwards, we give a detailed case study, which shows the effectiveness of reducing power consumption for the proposed layered C-IoT architecture. Additionally, for real-time and non-real-time applications, the power consumption of different on-off states for MTC devices is discussed.


Author(s):  
Christopher Teh Jun Qian ◽  
Micheal Drieberg ◽  
Patrick Sebastian ◽  
Azrina Abd Aziz ◽  
Hai Hiung Lo ◽  
...  

Currently, there is lack of implementation of practical power-saving schemes in most of the batteries powered by IoT smart city applications available in the market that can extend the battery lifetime, even though numerous researches have been carried to reduce the average power consumption. This is because electronics consume similar amounts of power during the idling state as compared to the active state, resulting in low power efficiency of the application. Thus, power consumption is affected by the modes of the electronic operations. Different electronics also have their own types of settings that can be configured to reduce the power consumption, and this will be further investigated in this study. This chapter will address the issue of how to create a power-saving IoT application by applying power-saving schemes and creating an accurate model to predict the battery lifetime of the IoT application.


2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.


Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.


Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.


2012 ◽  
Vol 512-515 ◽  
pp. 1295-1298
Author(s):  
De Feng Ding ◽  
Shi Jie Liu ◽  
Chao Yu Zheng ◽  
Wen Sheng Yu ◽  
Wu Chen

A general air-source heat pump water heater originally designed to work with R134a was reconstructed as experimental rig for performance studies on systems using different refrigerants including R32, R134a and the mixture of R32/R134a which mass ratio is 1:5. Experimental results showed that the power consumption of the heat pump water heater charged individually with R32 would greatly exceed the system’s original pre-set maximum input power. When the leaving water temperature was increased from 18°C to 58°C, the average discharge temperature of the heat pump charged with R32/R134a mixture was 13.6% higher than that with R134a. The average power consumption of the heat pump with R134a was 253.5W less than that with R32/R134a mixture. However, the average COP (Coefficient of Performance) obtained by that with R32/R134a mixture was 0.83 higher than that with R134a.


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