scholarly journals Temperature Sensor Assisted Lifetime Enhancement of Satellite Embedded Systems via Multi-Core Task Mapping and DVFS

Sensors ◽  
2019 ◽  
Vol 19 (22) ◽  
pp. 4902 ◽  
Author(s):  
Beomsik Kim ◽  
Hoeseok Yang
Keyword(s):  
Embedded Systems ◽  
High Performance ◽  
High Capacity ◽  
Low Earth Orbit ◽  
Task Mapping ◽  
Solar Panels ◽  
Satellite Systems ◽  
Weight Problems ◽  
Dynamic Voltage ◽  
Core Mapping

Recently, thanks to the miniaturization and high performance of commercial-off-the-shelf(COTS) computer systems, small satellites get popular. However, due to the very expensive launchingcost, it is critical to reduce the physical size and weight of the satellite systems such as cube satellites(CubeSats), making it infeasible to install high capacity batteries or solar panels. Thus, the low-powerdesign is one of the most critical issues in the design of such systems. In addition, as satellitesmake a periodic revolution around the Earth in a vacuum, their operating temperature varies greatly.For instance, in a low earth orbit (LEO) CubeSats, the temperatures vary from 30 to -30 degreesCelsius, resulting in a big thermal cycle (TC) in the electronic parts that is known to be one of themost critical reliability threats. Moreover, such LEO CubeSats are not fully protected by activethermal control and thermal insulation due to the cost, volume, and weight problems. In thispaper, we propose to utilize temperature sensors to maximize the lifetime reliability of the LEOsatellite systems via multi-core mapping and dynamic voltage and frequency scaling (DVFS) underpower constraint. As conventional reliability enhancement techniques primarily focus on reducingthe temperature, it may cause enlarged TCs, making them even less reliable. On the contrary,we try to maintain the TC optimal in terms of reliability with respect to the given power constraint.Experimental evaluation shows that the proposed technique improves the expected lifetime of thesatellite embedded systems by up to 8.03 times in the simulation of Nvidia’s Jetson TK1.

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

Denaturing High Performance Liquid Chromatography and Bioinformatics - Two Modern Tools for Extracellular Superoxide Dismutase (SOD3) Gene Promoter Analysis

2008 ◽  
Vol 59 (7) ◽  
Author(s):  
Corina Samoila ◽  
Alfa Xenia Lupea ◽  
Andrei Anghel ◽  
Marilena Motoc ◽  
Gabriela Otiman ◽  
...  
Keyword(s):  
High Performance Liquid Chromatography ◽  
Transcription Factors ◽  
Liquid Chromatography ◽  
Dna Sequences ◽  
High Performance ◽  
Zinc Finger Protein ◽  
High Capacity ◽  
Gene Promoter ◽  
Experimental Approaches ◽  
Myeloid Zinc Finger

Denaturing High Performance Liquid Chromatography (DHPLC) is a relatively new method used for screening DNA sequences, characterized by high capacity to detect mutations/polymorphisms. This study is focused on the Transgenomic WAVETM DNA Fragment Analysis (based on DHPLC separation method) of a 485 bp fragment from human EC-SOD gene promoter in order to detect single nucleotide polymorphism (SNPs) associated with atherosclerosis and risk factors of cardiovascular disease. The fragment of interest was amplified by PCR reaction and analyzed by DHPLC in 100 healthy subjects and 70 patients characterized by atheroma. No different melting profiles were detected for the analyzed DNA samples. A combination of computational methods was used to predict putative transcription factors in the fragment of interest. Several putative transcription factors binding sites from the Ets-1 oncogene family: ETS member Elk-1, polyomavirus enhancer activator-3 (PEA3), protein C-Ets-1 (Ets-1), GABP: GA binding protein (GABP), Spi-1 and Spi-B/PU.1 related transcription factors, from the Krueppel-like family: Gut-enriched Krueppel-like factor (GKLF), Erythroid Krueppel-like factor (EKLF), Basic Krueppel-like factor (BKLF), GC box and myeloid zinc finger protein MZF-1 were identified in the evolutionary conserved regions. The bioinformatics results need to be investigated further in others studies by experimental approaches.

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

scholarly journals Nanostructured intermetallic InSb as a high-capacity and high-performance negative electrode for sodium-ion batteries

2021 ◽  
Author(s):  
Irshad Mohammad ◽  
Lucie Blondeau ◽  
Eddy Foy ◽  
Jocelyne Leroy ◽  
Eric Leroy ◽  
...  
Keyword(s):  
Intermetallic Compound ◽  
High Performance ◽  
High Capacity ◽  
Negative Electrode ◽  
Sodium Ion ◽  
Sodium Ion Batteries ◽  
Negative Electrodes ◽  
First Time

Following the trends of alloys as negative electrodes for Na-ion batteries, the sodiation of the InSb intermetallic compound was investigated for the first time. The benefit of coupling Sb with...

scholarly journals GNSS RTK Positioning Augmented with Large LEO Constellation

2019 ◽  
Vol 11 (3) ◽  
pp. 228 ◽  
Author(s):  
Xingxing Li ◽  
Hongbo Lv ◽  
Fujian Ma ◽  
Xin Li ◽  
Jinghui Liu ◽  
...  
Keyword(s):  
Low Earth Orbit ◽  
Global Navigation Satellite Systems ◽  
Convergence Time ◽  
Current Status ◽  
Initial Assessment ◽  
Satellite Systems ◽  
Long Baseline ◽  
Leo Satellites ◽  
Global Navigation Satellite ◽  
Long Baselines

It is widely known that in real-time kinematic (RTK) solution, the convergence and ambiguity-fixed speeds are critical requirements to achieve centimeter-level positioning, especially in medium-to-long baselines. Recently, the current status of the global navigation satellite systems (GNSS) can be improved by employing low earth orbit (LEO) satellites. In this study, an initial assessment is applied for LEO constellations augmented GNSS RTK positioning, where four designed LEO constellations with different satellite numbers, as well as the nominal GPS constellation, are simulated and adopted for analysis. In terms of aforementioned constellations solutions, the statistical results of a 68.7-km baseline show that when introducing 60, 96, 192, and 288 polar-orbiting LEO constellations, the RTK convergence time can be shortened from 4.94 to 2.73, 1.47, 0.92, and 0.73 min, respectively. In addition, the average time to first fix (TTFF) can be decreased from 7.28 to 3.33, 2.38, 1.22, and 0.87 min, respectively. Meanwhile, further improvements could be satisfied in several elements such as corresponding fixing ratio, number of visible satellites, position dilution of precision (PDOP) and baseline solution precision. Furthermore, the performance of the combined GPS/LEO RTK is evaluated over various-length baselines, based on convergence time and TTFF. The research findings show that the medium-to-long baseline schemes confirm that LEO satellites do helpfully obtain faster convergence and fixing, especially in the case of long baselines, using large LEO constellations, subsequently, the average TTFF for long baselines has a substantial shortened about 90%, in other words from 12 to 2 min approximately by combining with the larger LEO constellation of 192 or 288 satellites. It is interesting to denote that similar improvements can be observed from the convergence time.

scholarly journals Plasmonic semiconductor nanogroove array enhanced broad spectral band millimetre and terahertz wave detection

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Jinchao Tong ◽  
Fei Suo ◽  
Tianning Zhang ◽  
Zhiming Huang ◽  
Junhao Chu ◽  
...  
Keyword(s):  
Surface Plasmon ◽  
High Performance ◽  
Room Temperature ◽  
Spectral Band ◽  
High Capacity ◽  
Terahertz Wave ◽  
Semiconductor Surface ◽  
Wide Range ◽  
Low Sensitivity ◽  
Air Interfaces

AbstractHigh-performance uncooled millimetre and terahertz wave detectors are required as a building block for a wide range of applications. The state-of-the-art technologies, however, are plagued by low sensitivity, narrow spectral bandwidth, and complicated architecture. Here, we report semiconductor surface plasmon enhanced high-performance broadband millimetre and terahertz wave detectors which are based on nanogroove InSb array epitaxially grown on GaAs substrate for room temperature operation. By making a nanogroove array in the grown InSb layer, strong millimetre and terahertz wave surface plasmon polaritons can be generated at the InSb–air interfaces, which results in significant improvement in detecting performance. A noise equivalent power (NEP) of 2.2 × 10−14 W Hz−1/2 or a detectivity (D*) of 2.7 × 1012 cm Hz1/2 W−1 at 1.75 mm (0.171 THz) is achieved at room temperature. By lowering the temperature to the thermoelectric cooling available 200 K, the corresponding NEP and D* of the nanogroove device can be improved to 3.8 × 10−15 W Hz−1/2 and 1.6 × 1013 cm Hz1/2 W−1, respectively. In addition, such a single device can perform broad spectral band detection from 0.9 mm (0.330 THz) to 9.4 mm (0.032 THz). Fast responses of 3.5 µs and 780 ns are achieved at room temperature and 200 K, respectively. Such high-performance millimetre and terahertz wave photodetectors are useful for wide applications such as high capacity communications, walk-through security, biological diagnosis, spectroscopy, and remote sensing. In addition, the integration of plasmonic semiconductor nanostructures paves a way for realizing high performance and multifunctional long-wavelength optoelectrical devices.

scholarly journals A germanium and zinc chalcogenide as an anode for a high-capacity and long cycle life lithium battery

RSC Advances ◽  
2019 ◽  
Vol 9 (60) ◽  
pp. 35045-35049
Author(s):  
Xu Chen ◽  
Jian Zhou ◽  
Jiarui Li ◽  
Haiyan Luo ◽  
Lin Mei ◽  
...  
Keyword(s):  
Energy Storage ◽  
High Performance ◽  
Lithium Battery ◽  
Large Scale ◽  
High Capacity ◽  
Lithium Ion ◽  
Energy Storage Devices ◽  
Storage Devices ◽  
Long Cycle Life ◽  
Zinc Chalcogenide

High-performance lithium ion batteries are ideal energy storage devices for both grid-scale and large-scale applications.

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