scholarly journals Low Power Contactless Voltage Sensor for Low Voltage Power Systems

Sensors ◽  
2019 ◽  
Vol 19 (16) ◽  
pp. 3513 ◽  
Author(s):  
Antonio Delle Femine ◽  
Daniele Gallo ◽  
Carmine Landi ◽  
Alessandro Lo Schiavo ◽  
Mario Luiso

Contactless measurements represent the desirable solution in many contexts, where minimal cabling is required or, in general, cabling is not possible. This paper presents a new contactless voltage sensor for low voltage power systems. It is based on a contactless capacitive probe, which surrounds the power cable. It has two concentric electrodes insulated by a shield. A low power analog conditioning circuit evaluates the power line voltage by measuring the current in one of the capacitances of the probe. All the single stages of the circuit have been designed by using low-power rail-to-rail operational amplifiers, supplied at 3.3 V, in order to minimize the power absorption. The sensor has been characterized in various conditions, with sine waves and distorted signals, varying the frequency and the harmonic distortion. The influence of the current, flowing into the power cable, on the voltage measurement has been evaluated too. It shows a good accuracy (lower than 0.3%) from 100 V to 300 V, with a power consumption less than 5 mW.

2015 ◽  
Vol 781 ◽  
pp. 296-299 ◽  
Author(s):  
Weerachat Khuleedee ◽  
Arkom Kaewrawang ◽  
Kittipong Tonmitr

This paper presents the impact of on-grid solar PV rooftop on local power systems of 10 kW - typical low voltage power rating for households campaigned by Thai Government. The overvoltage, frequency variation and harmonic contamination was investigated and analyzed. The condition of peak power generated from PV was also considered. The experimental data used for the analysis were collected by turning on and off the solar PV system of PEA power system on Udonthani province, Thailand for every hour with duration time between 6.00 AM and 6.00 PM. The results showed that the voltage at the connecting point of solar PV rooftop to the grid increases from 5-8 V (2.3-3.6%.).The frequency slightly increases from 49.97-50.06 Hz. In addition, the total harmonic distortion is not significantly different - varying in narrow range of 0.1-0.2 VTHD.


Energies ◽  
2020 ◽  
Vol 14 (1) ◽  
pp. 133
Author(s):  
Dawid Buła ◽  
Dariusz Grabowski ◽  
Michał Lewandowski ◽  
Marcin Maciążek ◽  
Anna Piwowar

The paper is related to the problem of modeling and optimizing power systems supplying, among others, nonlinear loads. A software solution that allows the modeling and simulation of power systems in the frequency domain as well as the sizing and allocation of active power filters has been developed and presented. The basic assumptions for the software development followed by the models of power system components and the optimization assumptions have been described in the paper. On the basis of an example of a low-voltage network, an analysis of the selection of the number and allocation of active power filters was carried out in terms of minimizing losses and investment costs under the assumed conditions for voltage total harmonic distortion (THD) coefficients in the network nodes. The presented examples show that the appropriate software allows for an in-depth analysis of possible solutions and, furthermore, the selection of the optimal one for a specific case, depending on the adopted limitations, expected effects, and investment costs. In addition, a very high computational efficiency of the adopted approach to modeling and simulation has been demonstrated, despite the use of (i) element models for which parameters depend on the operating point (named iterative elements), (ii) active filter models taking into account real harmonics reduction efficiency and power losses, and (iii) a brute force algorithm for optimization.


2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).


Sign in / Sign up

Export Citation Format

Share Document