scholarly journals An Analog Interface Circuit for Capacitive Angle Encoder Based on a Capacitance Elimination Array and Synchronous Switch Demodulation Method

Sensors ◽  
2019 ◽  
Vol 19 (14) ◽  
pp. 3116 ◽  
Author(s):  
Bo Hou ◽  
Bin Zhou ◽  
Xiang Li ◽  
Zhenyi Gao ◽  
Qi Wei ◽  
...  
Keyword(s):  
Power Consumption ◽  
Integrated Circuit ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Interface Circuit ◽  
Machine Systems ◽  
Sensitive Structure ◽  
Angle Encoder ◽  
Low Supply Voltage ◽  
Control Machine

This paper presents an analog interface application-specific integrated circuit (ASIC) for a capacitive angle encoder, which is widely used in control machine systems. The encoder consists of two parts: a sensitive structure and analog readout circuit. To realize miniaturization, low power consumption, and easy integration, an analog interface circuit including a DC capacitance elimination array and switch synchronous demodulation module was designed. The DC capacitance elimination array allows the measurement circuit to achieve a very high capacitance to voltage conversion ratio at a low supply voltage. Further, the switch synchronous demodulation module effectively removes the carrier signal and greatly reduces the sampling rate requirement of the analog-to-digital converter (ADC). The ASIC was designed and fabricated with standard 0.18 µm CMOS processing technology and integrated with the sensitive structure. An experiment was conducted to test and characterize the performance of the proposed analog interface circuit. The encoder measurement results showed a resolution of 0.01°, power consumption of 20 mW, and accuracy over the full absolute range of 0.1°, which indicates the great potential of the encoder for application in control machine systems.

A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA

2013 ◽  
Vol 22 (10) ◽  
pp. 1340033 ◽  
Author(s):  
HONGLIANG ZHAO ◽  
YIQIANG ZHAO ◽  
YIWEI SONG ◽  
JUN LIAO ◽  
JUNFENG GENG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Readout Integrated Circuit ◽  
Chip Area ◽  
Operating Modes

A low power readout integrated circuit (ROIC) for 512 × 512 cooled infrared focal plane array (IRFPA) is presented. A capacitive trans-impedance amplifier (CTIA) with high gain cascode amplifier and inherent correlated double sampling (CDS) configuration is employed to achieve a high performance readout interface for the IRFPA with a pixel size of 30 × 30 μm2. By optimizing column readout timing and using two operating modes in column amplifiers, the power consumption is significantly reduced. The readout chip is implemented in a standard 0.35 μm 2P4M CMOS technology. The measurement results show the proposed ROIC achieves a readout rate of 10 MHz with 70 mW power consumption under 3.3 V supply voltage from 77 K to 150 K operating temperature. And it occupies a chip area of 18.4 × 17.5 mm2.

A Low-Power, Signal-Specific SAR ADC for Neural Sensing Applications

2018 ◽  
Vol 27 (14) ◽  
pp. 1850230 ◽  
Author(s):  
Samaneh Babayan-Mashhadi ◽  
Mona Jahangiri-Khah
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Power Saving ◽  
Cmos Technology ◽  
Sar Adc ◽  
Signal Acquisition ◽  
Quantization Scheme ◽  
Power Efficient ◽  
Sensing Applications

As power consumption is one of the major issues in biomedical implantable devices, in this paper, a novel quantization method is proposed for successive approximation register (SAR) analog-to-digital converters (ADCs) which can save 80% power consumption in contrast to conventional structure for electroencephalogram (EEG) signal recording systems. According to the characteristics of neural signals, the principle of the proposed power saving technique was inspired such that only the difference between current input sample and the previous one is quantized, using a power efficient SAR ADC with fewer resolutions. To verify the proposed quantization scheme, the ADC is systematically modeled in Matlab and designed and simulated in circuit level using 0.18[Formula: see text][Formula: see text]m CMOS technology. When applied to neural signal acquisition, spice simulations show that at sampling rate of 25[Formula: see text]kS/s, the proposed 8-bit ADC consumes 260[Formula: see text]nW of power from 1.8[Formula: see text]V supply voltage while achieving 7.1 effective number of bits.

A low power-integrated temperature sensor interface circuit

2022 ◽  
Author(s):  
Mingyuan Ren ◽  
Huijing Yang ◽  
Beining Zhang ◽  
Guoxu Zheng
Keyword(s):  
Temperature Sensor ◽  
Supply Voltage ◽  
Sampling Rate ◽  
Average Power ◽  
Temperature Sensitive ◽  
Frequency Noise ◽  
Power Supply Voltage ◽  
Sensor Interface ◽  
Interface Circuit ◽  
Average Power Consumption

This paper constructs and simulates the interface circuit of a temperature sensor based on SMIC 0.18 [Formula: see text]m CMOS. The simulation results show that when the power supply voltage is 1.8 V, the chopper op-amp gain is 89.44 dB, the low-frequency noise is 71.83 nV/Hz,[Formula: see text] and the temperature coefficient of the core temperature sensitive circuit is 1.7808 mV/[Formula: see text]C. The sampling rate of 10-bit SAR ADC was 10 kS/s, effective bit was 9.0119, SNR was 59.3256 dB, SFDR was 68.7091 dB, and THD was −62.5859 dB. The measurement range of temperature sensor interface circuit is −50[Formula: see text]C[Formula: see text]C, the relative temperature measurement error is ±0.47[Formula: see text]C, the resolution is 0.2[Formula: see text]C/LSB, and the overall average power consumption is 434.9 [Formula: see text]W.

scholarly journals Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

2021 ◽  
Vol 27 (2) ◽  
pp. 31-39
Author(s):  
Jakob K. Toft ◽  
Ivan H. H. Jorgensen
Keyword(s):  
Power Consumption ◽  
Mechanical System ◽  
High Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Micro Electro Mechanical System ◽  
Silicon On Insulator ◽  
High Bias ◽  
Low Supply Voltage ◽  
Very High

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm silicon-on-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.

scholarly journals Robust 12T Sram Cell Using 45nm Technology

2020 ◽  
pp. 170-174
Author(s):  
N. Geetha Rani ◽  
N. Jyothi ◽  
P. Leelavathi ◽  
P. Deepthi Swarupa Rani ◽  
S. Reshma
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Leakage Power ◽  
Sram Cell ◽  
Static Power ◽  
Low Supply Voltage ◽  
Multi Core Processor

SRAM cells are used in many applications such as micro and multi core processor. SRAM cell improves both read stability and write ability at low supply voltage. The objective is to reduce the power dissipation of a novel low power 12T SRAM cell. This method removes half-select issue in 6T and 9T SRAM cell. This work proposes new functional low-power designs of SRAM cells with 6T, 9T and 12 transistors which operate at only 0.4V power supply in sub-threshold operation at 45 nm technology. The leakage power consumption of the proposed SRAM cell is thereby reduced compared to that of the conventional six-transistor (6T) SRAM cell. 12T cell obtains low static power dissipation.

A BISECTION-BASED POWER REDUCTION DESIGN FOR CMOS FLASH ANALOG-TO-DIGITAL CONVERTERS

2009 ◽  
Vol 18 (05) ◽  
pp. 933-945
Author(s):  
CHIA-CHUN TSAI ◽  
KAI-WEI HONG ◽  
TRONG-YEN LEE
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Clock Cycle ◽  
Sampling Rate ◽  
Reducing Power ◽  
Power Reduction ◽  
Analog To Digital Converters ◽  
Bisection Method ◽  
Flash Adc ◽  
Analog To Digital

In this paper, we present a bisection-based power reduction design for CMOS flash analog-to-digital converters (ADCs). A comparator-based inverter is employed along with two switches of an NMOS and a PMOS, the bisection method can let only half of comparators in a flash ADC work in every clock cycle for reducing power consumption. A practical example of 6-bit flash ADC operates at 200 MHz sampling rate and 3.3 V supply voltage is demonstrated. The power consumption of proposed circuit is only 40.75 mW with HSPICE simulation. Compared with the traditional flash ADC, our bisection method can reduce up to 43.18% in terms of power dissipation.

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