scholarly journals Design and Fabrication Technology of Low Profile Tactile Sensor with Digital Interface for Whole Body Robot Skin

Sensors ◽  
2018 ◽  
Vol 18 (7) ◽  
pp. 2374 ◽  
Author(s):  
Mitsutoshi Makihata ◽  
Masanori Muroyama ◽  
Shuji Tanaka ◽  
Takahiro Nakayama ◽  
Yutaka Nonomura ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Integrated Circuit ◽  
Tactile Sensor ◽  
Force Sensor ◽  
Whole Body ◽  
Capacitance Measurement ◽  
Device Structure ◽  
Local Pressure ◽  
Novel Device ◽  
Low Profile

Covering a whole surface of a robot with tiny sensors which can measure local pressure and transmit the data through a network is an ideal solution to give an artificial skin to robots to improve a capability of action and safety. The crucial technological barrier is to package force sensor and communication function in a small volume. In this paper, we propose the novel device structure based on a wafer bonding technology to integrate and package capacitive force sensor using silicon diaphragm and an integrated circuit separately manufactured. Unique fabrication processes are developed, such as the feed-through forming using a dicing process, a planarization of the Benzocyclobutene (BCB) polymer filled in the feed-through and a wafer bonding to stack silicon diaphragm onto ASIC (application specific integrated circuit) wafer. The ASIC used in this paper has a capacitance measurement circuit and a digital communication interface mimicking a tactile receptor of a human. We successfully integrated the force sensor and the ASIC into a 2.5 × 2.5 × 0.3 mm die and confirmed autonomously transmitted packets which contain digital sensing data with the linear force sensitivity of 57,640 Hz/N and 10 mN of data fluctuation. A small stray capacitance of 1.33 pF is achieved by use of 10 μm thick BCB isolation layer and this minimum package structure.

MEMS-CMOS Integrated Tactile Sensor with Digital Signal Processing for Robot Application

2012 ◽  
Vol 1427 ◽  
Author(s):  
M. Makihata ◽  
M. Muroyama ◽  
S. Tanaka ◽  
H. Yamada ◽  
T. Nakayama ◽  
...  
Keyword(s):  
Signal Processing ◽  
Digital Signal ◽  
Tactile Sensor ◽  
Force Sensor ◽  
Digital Data ◽  
Wafer Level ◽  
Tactile Sensors ◽  
Low Profile ◽  
Chip Size ◽  
Tactile Receptor

ABSTRACTAn ultra-small tactile sensor with functions of signal processing and digital communication has been prototyped based on MEMS-CMOS integration technology. The designed analog-digital mixed signal ASIC allows many tactile sensors to connect each other on a common bus line, which drastically reduces the number of wire. The ASIC capacitively detects the deformation of a force sensor and sends digital data to the common bus line when the force exceeds a threshold. The digital data contain a physical ID of each sensor, 32-bit sensing data and 16-bit cyclic redundancy check (CRC) code. In this study, a novel wafer-level integration and packaging technology were developed, and a chip-size-packaged tactile sensor with a small footprint (2.5mm×2.5mm) and a low profile (0.27mm) was prototyped and tested. The sensor autonomously sends digital data like a tactile receptor of human.

Enhanced output of ZnO nanosheet-based piezoelectric nanogenerator with a novel device structure

2021 ◽  
Author(s):  
Siju Mishra ◽  
P. Supraja ◽  
Vishnu V. Jaiswal ◽  
P. Ravi Sankar ◽  
R. Rakesh Kumar ◽  
...  
Keyword(s):  
Output Voltage ◽  
Photoluminescence Property ◽  
Cost Effective ◽  
Design Strategy ◽  
Aluminum Substrate ◽  
Device Structure ◽  
Novel Device ◽  
Voltage Output ◽  
Zno Nanosheets ◽  
Side Coating

Abstract We report the double-fold enhancement of piezoelectric nanogenerator output voltage with a simple design strategy. The piezoelectric nanogenerator is fabricated with ZnO nanosheets coated on both sides of the aluminum substrate in this new design strategy with necessary electrodes. The cost-effective hydrothermal method is employed to synthesize two-dimensional (2D) ZnO nanosheets on both sides of the aluminum substrate at a low growth temperature of 80˚C for 4 hours. The ZnO nanosheets were characterized for their morphology, crystallinity, and photoluminescence property. The nanogenerator is fabricated with a double-side coated aluminum substrate and compared its performance with a single-side coated aluminum substrate. The nanogenerators fabricated only with one side coating produced an output voltage of ~ 170 mV. In contrast, the nanogenerators fabricated with a double side coating produced an output voltage of ~ 285 mV. The nanogenerator with double-side coating produced ~1.7 times larger voltage output compared to the voltage output from one side coated nanogenerators fabricated with each side of the substrate. The enhancement in the output

Room-Temperature Wafer Bonded Multi-Junction Solar Cell Grown by Solid State Molecular Beam Epitaxy

MRS Advances ◽  
2016 ◽  
Vol 1 (43) ◽  
pp. 2907-2916 ◽  
Author(s):  
Shulong Lu ◽  
Shiro Uchida
Keyword(s):  
Solar Cell ◽  
Molecular Beam Epitaxy ◽  
Wafer Bonding ◽  
Room Temperature ◽  
Molecular Beam ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Short Circuit Current Density ◽  
Device Structure ◽  
Junction Solar Cell

ABSTRACTWe studied the InGaP/GaAs//InGaAsP/InGaAs four-junction solar cells grown by molecular beam epitaxy (MBE), which were fabricated by the novel wafer bonding. In order to reach a higher conversion efficiency at highly concentrated illumination, heat generation should be minimized. We have improved the device structure to reduce the thermal and electrical resistances. Especially, the bond resistance was reduced to be the lowest value of 2.5 × 10-5 Ohm cm2 ever reported for a GaAs/InP wafer bond, which was obtained by the specific combination of p+-GaAs/n-InP bonding and by using room-temperature wafer bonding. Furthermore, in order to increase the short circuit current density (Jsc) of 4-junction solar cell, we have developed the quality of InGaAsP material by increasing the growth temperature from 490 °C to 510 °C, which leads to a current matching. In a result, an efficiency of 42 % at 230 suns of the four-junction solar cell fabricated by room-temperature wafer bonding was achieved.

Enhancement of ESD performances of Silicon Capacitors for RFID solutions

2020 ◽  
Vol 2020 (1) ◽  
pp. 000085-000089
Author(s):  
Sébastien Jacqueline ◽  
Catherine Bunel ◽  
Laurent Lengignon
Keyword(s):  
Cross Sections ◽  
Radio Frequency Identification ◽  
Integrated Circuit ◽  
Equivalent Series Resistance ◽  
Human Body Model ◽  
Capacitance Density ◽  
Electrical Failure ◽  
Low Profile ◽  
Lc Circuit ◽  
Process Architecture

Abstract Radio-Frequency IDentification devices such as smart cards and RFID tags are based on the presence of a resonant tuned LC circuit associated to the RFID Integrated Circuit (IC). The use of discrete capacitor, external to the IC gives greater flexibility and design freedom. In the race of miniaturization, manufacturers of RFID devices always require smaller electronic components. To save space and in the same time improve performances, capacitors are exposed to height and volume constraints. In the same time, the capacitor has to withstand ESD stresses that can occur during the assembly of the device and during operation. Murata has developed a unique thin capacitor technology in silicon. This paper reports the development of a range of low profile capacitors with enhanced ESD performances. The manufacturing process optimization and the design adjustments will be presented here. The process was optimized by taking into account the main electrical parameters: leakage current, breakdown voltage, capacitance density, capacitance accuracy, Equivalent Series Resistance (ESR) and Self-Resonant Frequency (SRF). The dielectric stack was defined in order to integrate up to 330pF in 0402 case. The process architecture, based on accurate planar capacitor with thick dielectric will be discussed. With this architecture there is no constraint to reach low thickness, such as 100μm or even lower. The ESD threshold of each Silicon Capacitor was investigated with design variations associated to Human Body Model measurements. A Single Project Wafer (SPW) was founded with 36 different capacitor designs. Design modulations specifically addressed the orientation and position of the contacts openings. Special care was taken to maximize the width of the contact holes and metal tracks. A mosaic approach, constructed out of a massive network of parallelized elementary cells was also implemented, so that the charges of the ESD pulse do not concentrate at the same place, leading to electrical failure. Examples of defects due to ESD stress will be shown with failure analysis cross-sections and ways to enhance the ESD threshold by design will be illustrated.

“Cleaning”- The Dirty Word in Packaging Assembly

2010 ◽  
Vol 2010 (1) ◽  
pp. 000742-000746
Author(s):  
Rich Brooks
Keyword(s):  
Thermal Energy ◽  
Integrated Circuit ◽  
Flip Chip ◽  
New Technologies ◽  
Cleaning Process ◽  
Maximum Performance ◽  
Low Profile ◽  
Total Process ◽  
Temperature And Pressure

A majority of the package assembly facilities are using only DI water to remove flux residue from under flip-chip devices, prior to an underfill process. As the new technologies are being implemented, not only has DI water reached its limitations, but some cleaning chemistries are not able to perform adequately to remove ALL of the flux residues. Complete cleaning and removal of the flux residues under low profile components are critical to maintain the reliability of the integrated circuit. Therefore, the cleaning process must be carefully examined and optimized to obtain maximum performance for removing the flux residues. The total cleaning process can be broken down into two subsets:Static Cleaning rate & Dynamic Cleaning rate The Static Cleaning rate is ability of the cleaning chemistry to remove or dissolve the residue in the absence of temperature and pressure. The Dynamic Cleaning rate involves the kinetic forces and energy to remove the residue. This includes the Thermal energy and Impingement energy required to remove the flux residue. The sum of these two cleaning rates (Static and Dynamic cleaning rates) equal the Total Process Cleaning rate (see formula below). This paper will review cleaning problems brought about with the implementation of the latest technologies and explain how the cleaning process can be optimized to guarantee the reliability of the assemblies.

Novel device structure for phase change memory toward low-current operation

2015 ◽  
Vol 54 (9) ◽  
pp. 094302 ◽  
Author(s):  
Eunha Kim ◽  
Nam Soo Kang ◽  
Hyung-Jun Yang ◽  
Yuji Sutou ◽  
Yun-Heub Song
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Device Structure ◽  
Novel Device ◽  
Current Operation ◽  
Change Memory

Fluid Impact Under Various Tapping Conditions for Biomedical Application (Shirodhara)

2018 ◽  
Author(s):  
Swathika Meenraj ◽  
Chebolu Lakshmana Rao ◽  
Balasubramanian Venkatesh
Keyword(s):  
Integrated Circuit ◽  
Biomedical Application ◽  
Force Sensor ◽  
Intermittent Flow ◽  
Time Duration ◽  
Impact Experiment ◽  
Controlled Flow ◽  
Using Data ◽  
Short Time ◽  
The Impact

Shirodhara is an ayurveda therapy treating subjects for stress (depression/anxiety/hypertension) insomnia, headache and several kinds of psychosis. When there is a fluid impact on a solid surface, a transient impact will be developed at the interface in short time duration as vibration on forehead. The fluid impact of the liquid falling from the beaker at controlled flow rate is measured using an integrated circuit piezoelectric (ICP) force sensor for various tapping condition. The time-dependent response of the sensor is acquired using data acquisition system which is connected to the computer. The force is determined by measuring the voltage output from the piezoelectric force sensor. The impact experiment is done for single droplet, intermittent flow of drops and continuous flow of liquid falling from a fixed height of 7.5 cm. From the results, we observe the impact force for each fluid have a subtle variation depending on the falling condition and impact velocity of the fluid falling from a height.

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