scholarly journals High-Performance Motion Estimation for Image Sensors with Video Compression

Sensors ◽  
2015 ◽  
Vol 15 (8) ◽  
pp. 20752-20778 ◽  
Author(s):  
Weizhi Xu ◽  
Shouyi Yin ◽  
Leibo Liu ◽  
Zhiyong Liu ◽  
Shaojun Wei
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Image Sensors

An Improved Object-Based Video Segmentation Method

2012 ◽  
Vol 220-223 ◽  
pp. 2445-2449
Author(s):  
Wen Dan Xu ◽  
Xin Quan Lai ◽  
Dong Lai Xu
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Video Segmentation ◽  
Error Function ◽  
Least Square ◽  
Video Frame ◽  
Merging Process ◽  
Initial Segmentation ◽  
Two Stages

This paper presents an improved video segmentation scheme, which consists of two stages: initial segmentation and motion estimation. In the initial segmentation, the watershed transformation followed by a region adjacency graph guided region merging process is used to partition the first video frame into spatial homogenous regions. Then the motion of changed region is estimated. Based on the highly efficient quadratic motion model, the motion estimation is undertaken using Gauss-Newton Levenberg-Marquardt method to minimize the least-square error function. Experimental results show the proposed scheme provides high performance in terms of segmentation accuracy and video compression ratio.

High Performance Architecture of Motion Estimation Algorithm for Video Compression

2016 ◽  
Vol 25 (08) ◽  
pp. 1650083
Author(s):  
P. Muralidhar ◽  
C. B. Rama Rao
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
Estimation Algorithm ◽  
Block Matching ◽  
High Definition ◽  
Systolic Architecture ◽  
Hardware Architectures ◽  
Computationally Intensive ◽  
Full Search

Motion estimation (ME) is a highly computationally intensive operation in video compression. Efficient ME architectures are proposed in the literature. This paper presents an efficient low computational complexity systolic architecture for full search block matching ME (FSBME) algorithm. The proposed architecture is based on one-bit transform-based full search (FS) algorithm. The proposed ME hardware architectures perform FS ME for four macroblocks (MBs) in parallel. The proposed hardware architecture is implemented in VHDL. The FSBME hardware consumes 34% of the slices in a Xilinx Vertex XC6vlx240T FPGA device with a maximum frequency of 133[Formula: see text]MHz and is capable of processing full high definition (HD) ([Formula: see text]) frames at a rate of 60 frames per second.

scholarly journals High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

2019 ◽  
Vol 8 (6) ◽  
pp. 1235-1238
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Block Size ◽  
Video Encoding ◽  
Computational Time ◽  
Absolute Difference ◽  
Asymmetric Mode

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.

Parallel Full Search Algorithm for Motion Estimation on Graphic Processing Unit

2019 ◽  
Vol 12 (4) ◽  
pp. 317-323
Author(s):  
Fatma Ezzahra Sayadi ◽  
Marwa Chouchene ◽  
Haithem Bahri ◽  
Randa Khemiri ◽  
Mohamed Atri
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Performance ◽  
High Efficiency ◽  
Search Algorithm ◽  
Low Cost ◽  
Video Quality ◽  
Processing Unit ◽  
High Efficiency Video Coding ◽  
Nvidia Gpu

Background: Advances in video compression technology have been driven by everincreasing processing power available in software and hardware. Methods: The emerging High-Efficiency Video Coding (HEVC) standard aims to provide a doubling in coding efficiency with respect to the H.264/AVC high profile, delivering the same video quality at half the bit rate. Results: Thus, the results show high computational complexity. In both standards, the motion estimation block presents a significant challenge in clock latency since it consumes more than 40% of the total encoding time. For these reasons, we proposed an optimized implementation of this algorithm on a low-cost NVIDIA GPU developed with CUDA language. Conclusion: This optimized implementation can provide high-performance video encoder where the speed reaches about 85.

Adaptive Return Prediction Block Matching Algorithms for Video Coding

2011 ◽  
Vol 145 ◽  
pp. 277-281
Author(s):  
Vaci Istanda ◽  
Tsong Yi Chen ◽  
Wan Chun Lee ◽  
Yuan Chen Liu ◽  
Wen Yen Chen
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
Web Site ◽  
Motion Vector ◽  
Temporal Correlation ◽  
Block Matching ◽  
Asynchronous Learning ◽  
Learning And Teaching ◽  
Block Motion ◽  
Reconstruction Image

As the development of network learning, video compression is important for both data transmission and storage, especially in a digit channel. In this paper, we present the return prediction search (RPS) algorithm for block motion estimation. The proposed algorithm exploits the temporal correlation and characteristic of returning origin to obtain one or two predictive motion vector and selects one motion vector, which presents better result, to be the initial search center. In addition, we utilize the center-biased block matching algorithms to refine the final motion vector. Moreover, we used adaptive threshold technique to reduce the computational complexity in motion estimation. Experimental results show that RPS algorithm combined with 4SS, BBGDS, and UCBDS effectively improves the performance in terms of mean-square error measure with less average searching points. On the other hand, accelerated RPS (ARPS) algorithm takes only 38% of the searching computations than 3SS algorithm, and the reconstruction image quality of the ARPS algorithm is superior to 3SS algorithm about 0.30dB in average overall test sequences. In addition, we create an asynchronous learning environment which provides students and instructors flexibility in learning and teaching activities. The purpose of this web site is to teach and display our researchable results. Therefore, we believe this web site is one of the keys to help the modern student achieve mastery of complex Motion Estimation.

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