scholarly journals A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

Sensors ◽  
2015 ◽  
Vol 15 (7) ◽  
pp. 17076-17088 ◽  
Author(s):  
Diwei He ◽  
Stephen Morgan ◽  
Dimitrios Trachanis ◽  
Jan van Hese ◽  
Dimitris Drogoudis ◽  
...  
Keyword(s):  
Pulse Oximeter ◽  
Single Chip ◽  
On Chip ◽  
Lock In

scholarly journals A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽  
2021 ◽  
Vol 12 (2) ◽  
pp. 183
Author(s):  
Jose Ricardo Gomez-Rodriguez ◽  
Remberto Sandoval-Arechiga ◽  
Salvador Ibarra-Delgado ◽  
Viktor Ivan Rodriguez-Abdala ◽  
Jose Luis Vazquez-Avila ◽  
...  
Keyword(s):  
Single Chip ◽  
Synthesis Time ◽  
Networks On Chip ◽  
Data Dependencies ◽  
Layered Architecture ◽  
Systems On Chip ◽  
Challenges And Opportunities ◽  
Computing Platforms ◽  
On Chip ◽  
Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

scholarly journals An overview of on-chip buses

2006 ◽  
Vol 19 (3) ◽  
pp. 405-428 ◽  
Author(s):  
Milica Mitic ◽  
Mile Stojcev
Keyword(s):  
Interconnection Networks ◽  
Electronics Industry ◽  
Design Reuse ◽  
Design Teams ◽  
Single Chip ◽  
Data Transfers ◽  
System On A Chip ◽  
Design Interfaces ◽  
On Chip ◽  
Levels Of Integration

The electronics industry has entered the era of multi-million-gate chips, and there Xs no turning back. This technology promises new levels of integration on a single chip, called the System-on-a-Chip (SoC) design, but also presents significant challenges to the chip designer. Processing cores on a single chip, may number well into the high tens within the next decade, given the current rate of advancements, [1]. Interconnection networks in such an environment are, therefore, becoming more and more important [2]. Currently on-chip interconnection networks are mostly implemented using buses. For SoC applications, design reuse becomes easier if standard internal connection buses are used for interconnecting components of the design. Design teams developing modules intended for future reuse can design interfaces for the standard bus around their particular modules. This allows future designers to slot the reuse module into their new design simply, which is also based around the same standard bus [3]. In this paper we give an overview of the more popular on-chip bus-based interconnection networks such as AMBA, Avalon CoreConnect, STBus, Wishbone, etc. The main characteristics of the considered buses in respect to topology, arbitration method, bus-width, and types of data transfers are discussed.

Critical Issues of TSV and 3D IC Integration

2010 ◽  
Vol 7 (1) ◽  
pp. 35-43 ◽  
Author(s):  
John H. Lau
Keyword(s):  
System On Chip ◽  
The Other ◽  
Single Chip ◽  
3D Ic ◽  
Moore’S Law ◽  
Moore's Law ◽  
Other Hand ◽  
Critical Issues ◽  
Research Problems ◽  
On Chip

Moore's law has been the most powerful driver for the development of the microelectronic industry. This law is grounded in lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration. However, there are many critical issues for 3D IC integration. In this study, some of the critical issues will be discussed and some potential solutions or research problems will be proposed.

scholarly journals Microfluidic Flow-through SPME Chip for Online Separation and MS Detection of Multiple Analyses in Complex Matrix

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 120
Author(s):  
Yujun Chen ◽  
Tao Gong ◽  
Cilong Yu ◽  
Xiang Qian ◽  
Xiaohao Wang
Keyword(s):  
Microfluidic Chip ◽  
Solid Phase Microextraction ◽  
Solid Phase ◽  
Sample Pretreatment ◽  
Annular Channel ◽  
Calibration Method ◽  
Extraction Process ◽  
Single Chip ◽  
Calibration Methods ◽  
On Chip

Simplifying tedious sample preparation procedures to improve analysis efficiency is a major challenge in contemporary analytical chemistry. Solid phase microextraction (SPME), a technology developed for rapid sample pretreatment, has flexibility in design, geometry, and calibration strategies, which makes it a useful tool in a variety of fields, especially environmental and life sciences. Therefore, it is important to study the coupling between the microfluidic electrospray ionization (ESI) chip integrated with the solid phase microextraction (SPME) module and the electrospray mass spectrometer (MS). In our previous work, we designed a solid phase microextraction (SPME) module on a microfluidic chip through geometric design. However, automation and calibration methods for the extraction process remain unresolved in the SPME on-chip domain, which will lead to faster and more accurate results. This paper discusses the necessity to design a micromixer structure that can produce different elution conditions on the microfluidic chip. By calculating the channel resistances, the microfluidic chip’s integrated module with the micromixer, SPME, and ESI emitters optimize the geometry structure. We propose the annular channel for SPME to perform the resistances balance of the entire chip. Finally, for SPME on a single chip, this work provides a quantitation calibration method to describe the distribution of the analytes between the sample and the extraction phase before reaching the adsorption equilibrium.

An Internal Schematic View and Simulation of Major Diagonal Mesh Network-on-Chip

2019 ◽  
Vol 16 (10) ◽  
pp. 4412-4417 ◽  
Author(s):  
Sanjeev Kumar Sharma ◽  
Arpit Jain ◽  
Kamali Gupta ◽  
Devendra Prasad ◽  
Varinder Singh
Keyword(s):  
Network On Chip ◽  
Mesh Network ◽  
Network Architectures ◽  
Memory Usage ◽  
Semantic View ◽  
Single Chip ◽  
Register Transfer ◽  
On Chip ◽  
High Congestion

NoC is a competent communication for on chip network architectures. It make more efficient the computational and high congestion communication on a single chip. In this paper, we are proposing a NoC topologies, i.e., Major Diagonal Mesh NoC called MD-Mesh NoC. In MD-Mesh NoC the corner of major diagonal linked with each other so that the efficiency of the communication among the corner can be increase. The internal semantic view and register transfer logic (RTL) View has been shown. As number of connections among the nodes increases and number of hopes decreases, performance of packet traversing will get increases. The synthesis and simulation has been done on Vertex 5 FPGA. The hardware parameters like number of slices and memory usage with respect to increase the number of nodes has been calculated on FPGA Vertex 5.

TOWARD A MINIATURIZED GENERATION OF ULTRASONIC-BASED DEVICES

2007 ◽  
Vol 16 (06) ◽  
pp. 1027-1044
Author(s):  
ABDALLAH KASSEM ◽  
MOHAMAD SAWAN ◽  
MUSTAPHA HAMAD ◽  
ALI HAIDAR
Keyword(s):  
Real Time ◽  
Video Processing ◽  
Design Method ◽  
Minimum Size ◽  
Ultrasound Images ◽  
Single Chip ◽  
Digital Beamforming ◽  
Quadrature Demodulation ◽  
Angle Of View ◽  
On Chip

This paper concerns the design method and implementation of main modules, dedicated to miniaturized digital ultrasonic devices, using advanced System-on-Chip technique. It is intended to diagnostic imaging applications such as echography. The proposed implementation allows the integration of all acquisition front end as well as signal and video processing on only one single chip. It will make possible to visualize the ultrasound images in real time. It requires high resolution and real-time image processing. The proposed design, which integrates the B-mode processing modules, includes digital beamforming, quadrature demodulation of RF signals, digital filtering, envelope detection, and video processing of the received signals. This system handles 128 scan lines and 6400 samples per scan line with a 90° angle of view span. The design uses a minimum size look-up memory to store the initial scan information. Rapid prototyping based on ARM/FPGA platform combination is used to validate the operation of the described system. This system offers significant advantages of portability and a rapid time to market.

scholarly journals The translational roadmap of the gut models, focusing on gut-on-chip

2021 ◽  
Vol 1 ◽  
pp. 62
Author(s):  
Giulia Malaguarnera ◽  
Miriam Graute ◽  
Antoni Homs Corbera
Keyword(s):  
Gut Microbiota ◽  
Translational Research ◽  
Microfluidic Devices ◽  
Pathological Features ◽  
Single Chip ◽  
Pharmacological Tests ◽  
Intestinal Physiology ◽  
On Chip ◽  
Physiological Systems

It is difficult to model in vitro the intestine when seeking to include crosstalk with the gut microbiota, immune and neuroendocrine systems. Here we present a roadmap of the current models to facilitate the choice in preclinical and translational research with a focus on gut-on-chip. These micro physiological systems (MPS) are microfluidic devices that recapitulate in vitro the physiology of the intestine. We reviewed the gut-on-chips that had been developed in academia and industries as single chip and that have three main purpose: replicate the intestinal physiology, the intestinal pathological features, and for pharmacological tests.

scholarly journals Network-On-Chip Topologies: Potentials, Technical Challenges, Recent Advances and Research Direction

2021 ◽  
Author(s):  
Isiaka A. Alimi ◽  
Romil K. Patel ◽  
Oluyomi Aboderin ◽  
Abdelgader M. Abdalla ◽  
Ramoni A. Gbadamosi ◽  
...  
Keyword(s):  
High Performance ◽  
Research Direction ◽  
Network On Chip ◽  
Limiting Factor ◽  
Single Chip ◽  
Chip Design ◽  
Application Mapping ◽  
Technology Advancement ◽  
On Chip ◽  
Heterogeneous Cores

Integration technology advancement has impacted the System-on-Chip (SoC) in which heterogeneous cores are supported on a single chip. Based on the huge amount of supported heterogeneous cores, efficient communication between the associated processors has to be considered at all levels of the system design to ensure global interconnection. This can be achieved through a design-friendly, flexible, scalable, and high-performance interconnection architecture. It is noteworthy that the interconnections between multiple cores on a chip present a considerable influence on the performance and communication of the chip design regarding the throughput, end-to-end delay, and packets loss ratio. Although hierarchical architectures have addressed the majority of the associated challenges of the traditional interconnection techniques, the main limiting factor is scalability. Network-on-Chip (NoC) has been presented as a scalable and well-structured alternative solution that is capable of addressing communication issues in the on-chip systems. In this context, several NoC topologies have been presented to support various routing techniques and attend to different chip architectural requirements. This book chapter reviews some of the existing NoC topologies and their associated characteristics. Also, application mapping algorithms and some key challenges of NoC are considered.

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