scholarly journals Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

Sensors ◽  
2011 ◽  
Vol 11 (5) ◽  
pp. 4943-4971 ◽  
Author(s):  
Anthony H. D. Graham ◽  
Jon Robbins ◽  
Chris R. Bowen ◽  
John Taylor
Keyword(s):  
Integrated Circuit ◽  
Electrode Arrays ◽  
Cmos Integrated Circuit ◽  
Circuit Technology

scholarly journals Acquisition of Neural Action Potentials Using Rapid Multiplexing Directly at the Electrodes

Micromachines ◽  
2018 ◽  
Vol 9 (10) ◽  
pp. 477 ◽  
Author(s):  
Mohit Sharma ◽  
Avery Gardner ◽  
Hunter Strathman ◽  
David Warren ◽  
Jason Silver ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Neural Recording ◽  
Frequency Noise ◽  
Electrode Arrays ◽  
Analog To Digital ◽  
Engineering Research ◽  
Cmos Integrated Circuit ◽  
In Vivo Experiments ◽  
High Impedance

Neural recording systems that interface with implanted microelectrodes are used extensively in experimental neuroscience and neural engineering research. Interface electronics that are needed to amplify, filter, and digitize signals from multichannel electrode arrays are a critical bottleneck to scaling such systems. This paper presents the design and testing of an electronic architecture for intracortical neural recording that drastically reduces the size per channel by rapidly multiplexing many electrodes to a single circuit. The architecture utilizes mixed-signal feedback to cancel electrode offsets, windowed integration sampling to reduce aliased high-frequency noise, and a successive approximation analog-to-digital converter with small capacitance and asynchronous control. Results are presented from a 180 nm CMOS integrated circuit prototype verified using in vivo experiments with a tungsten microwire array implanted in rodent cortex. The integrated circuit prototype achieves <0.004 mm2 area per channel, 7 µW power dissipation per channel, 5.6 µVrms input referred noise, 50 dB common mode rejection ratio, and generates 9-bit samples at 30 kHz per channel by multiplexing at 600 kHz. General considerations are discussed for rapid time domain multiplexing of high-impedance microelectrodes. Overall, this work describes a promising path forward for scaling neural recording systems to numbers of electrodes that are orders of magnitude larger.

scholarly journals Skybridge-3D-CMOS: A Fine-Grained 3D CMOS Integrated Circuit Technology

2017 ◽  
Vol 16 (4) ◽  
pp. 639-652 ◽  
Author(s):  
Mingyu Li ◽  
Jiajun Shi ◽  
Mostafizur Rahman ◽  
Santosh Khasanvis ◽  
Sachin Bhat ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Cmos Integrated Circuit ◽  
Fine Grained ◽  
Circuit Technology

Preparation of TEM samples by focused ion beams

1995 ◽  
Vol 53 ◽  
pp. 518-519
Author(s):  
John F. Walker ◽  
J C Reiner ◽  
C Solenthaler
Keyword(s):  
Integrated Circuit ◽  
Polycrystalline Silicon ◽  
Field Effect Transistor ◽  
High Spatial Resolution ◽  
Ion Beam ◽  
Ion Beams ◽  
Focused Ion Beams ◽  
Precise Location ◽  
Effect Transistor ◽  
Circuit Technology

The high spatial resolution available from TEM can be used with great advantage in the field of microelectronics to identify problems associated with the continually shrinking geometries of integrated circuit technology. In many cases the location of the problem can be the most problematic element of sample preparation. Focused ion beams (FIB) have previously been used to prepare TEM specimens, but not including using the ion beam imaging capabilities to locate a buried feature of interest. Here we describe how a defect has been located using the ability of a FIB to both mill a section and to search for a defect whose precise location is unknown. The defect is known from electrical leakage measurements to be a break in the gate oxide of a field effect transistor. The gate is a square of polycrystalline silicon, approximately 1μm×1μm, on a silicon dioxide barrier which is about 17nm thick. The break in the oxide can occur anywhere within that square and is expected to be less than 100nm in diameter.

PERFORMANCE AT THE EDGE: GALLIUM ARSENIDE AND SILICON ICs FOR OPTICAL ELECTRONICS

1991 ◽  
Vol 02 (03) ◽  
pp. 147-162 ◽  
Author(s):  
ROBERT G. SWARTZ
Keyword(s):  
Gallium Arsenide ◽  
Optical Communication ◽  
Optical Communications ◽  
Integrated Circuit ◽  
High Performance ◽  
Compound Semiconductor ◽  
Performance Curve ◽  
Semiconductor Technology ◽  
Market Trends ◽  
Circuit Technology

Compound semiconductor technology is rapidly entering the mainstream, and is quickly finding its way into consumer applications where high performance is paramount. But silicon integrated circuit technology is evolving up the performance curve, and CMOS in particular is consuming ever more market share. Nowhere is this contest more clearly evident than in optical communications. Here applications demand performance ranging from a few hundreds of megahertz to multi-gigahertz, from circuits containing anywhere from tens to tens of thousands of devices. This paper reviews the high performance electronics found in optical communication applications from a technology standpoint, illustrating merits and market trends for these competing, yet often complementary IC technologies.

scholarly journals Design and Development of a 3dB Quadrature Patch Hybrid Coupler

2018 ◽  
Vol 7 (2.6) ◽  
pp. 217
Author(s):  
B Sekharbabu ◽  
K Narsimha Reddy ◽  
S Sreenu
Keyword(s):  
Integrated Circuit ◽  
High Frequency ◽  
Return Loss ◽  
Coupling Factor ◽  
Power Combiners ◽  
Measurement Results ◽  
Structure Simulation ◽  
Hybrid Coupler ◽  
Port Device ◽  
Circuit Technology

In this paper a -3 dB, 90-degreephase shift RF quadrature patch hybrid coupler is designed to operate at 2.4GHz. Hybrid coupler is a four-port device, that’s accustomed split a signaling with a resultant 90degrees’ section shift between output signals whereas maintaining high isolation between the output ports. The RF quadrature patch hybrid coupler is used in various radio frequency applications including mixers, power combiners, dividers, modulators and amplifiers. The desired hybrid coupler is designed using FR-4 substrate with 1.6mm height in High Frequency Structure Simulation (HFSS) and the same is fabricated and tested. The designed Hybrid coupler is examined in terms of parameters like insertion Loss, coupling factor and return Loss. The simulation and measurement results are compared. Major advantages of the RF quadrature patch hybrid couplers are that they are compatible with integrated circuit technology.

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