scholarly journals A Monolithic Three-Axis Accelerometer with Wafer-Level Package by CMOS MEMS Process

Proceedings ◽  
2017 ◽  
Vol 1 (4) ◽  
pp. 337 ◽  
Author(s):  
S. H. Tseng ◽  
C. Y. Yeh ◽  
A. Y. Chang ◽  
Y. J. Wang ◽  
P. C. Chen ◽  
...  
Keyword(s):  
Wafer Level ◽  
Cmos Mems ◽  
Wafer Level Package ◽  
Mems Process

Implementation of a monolithic capacitive accelerometer in a wafer-level 0.18 µm CMOS MEMS process

2012 ◽  
Vol 22 (5) ◽  
pp. 055010 ◽  
Author(s):  
Sheng-Hsiang Tseng ◽  
Michael S-C Lu ◽  
Po-Chang Wu ◽  
Yu-Chen Teng ◽  
Hann-Huei Tsai ◽  
...  
Keyword(s):  
Wafer Level ◽  
Capacitive Accelerometer ◽  
Cmos Mems ◽  
Mems Process

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

A Wafer-Level Packaged CMOS MEMS Pirani Vacuum Gauge

2021 ◽  
pp. 1-7
Author(s):  
Wei Xu ◽  
Xiaoyi Wang ◽  
Xiaofang Pan ◽  
Amine Bermak ◽  
Yi-Kuen Lee ◽  
...  
Keyword(s):  
Wafer Level ◽  
Vacuum Gauge ◽  
Cmos Mems
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