scholarly journals GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

Physics ◽  
2021 ◽  
Vol 4 (1) ◽  
pp. 1-11
Author(s):  
Pablo Dopazo ◽  
Carola de Benito ◽  
Oscar Camps ◽  
Stavros G. Stavrinides ◽  
Rodrigo Picos
Keyword(s):  
Parallel Algorithm ◽  
Field Programmable Gate Array ◽  
Computing Time ◽  
Scale Up ◽  
Delay Element ◽  
Optimal Paths ◽  
Field Programmable ◽  
Test Graph ◽  
Memristor Emulator ◽  
Game Changer

Memristive technology is a promising game-changer in computers and electronics. In this paper, a system exploring the optimal paths through a maze, utilizing a memristor-based setup, is developed and concreted on a FPGA (field-programmable gate array) device. As a memristor, a digital emulator has been used. According to the proposed approach, the memristor is used as a delay element, further configuring the test graph as a memristor network. A parallel algorithm is then applied, successfully reducing computing time and increasing the system’s efficiency. The proposed system is simple, easy to scale up and capable of implementing different graph configurations. The operation of the algorithm in the MATLAB (matrix laboratory) programming enviroment is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases, reliable results are obtained quickly and conveniently, even for the case of a 300 × 300 nodes maze.

scholarly journals GERARD: GEneral RApid Resolution of Digital Mazes Using a Memristor Emulator

2021 ◽  
Author(s):  
Pablo Dopazo ◽  
Carol de Benito ◽  
Oscar Camps ◽  
Stavros G. Stavrinides ◽  
Rodrigo Picos
Keyword(s):  
Parallel Algorithm ◽  
Computing Time ◽  
Delay Element ◽  
Rapid Resolution ◽  
Optimal Paths ◽  
Test Graph ◽  
Memristor Emulator ◽  
Increase Efficiency

In this paper, a system of searching for optimal paths is developed and concreted on a FPGA. It is based on a memristive emulator, used as a delay element, by configuring the test graph as a memristor network. A parallel algorithm is applied to reduce computing time and increase efficiency. The operation of the algorithm in Matlab is checked beforehand and then exported to two different Intel FPGAs: a DE0-Nano board and an Arria 10 GX 220 FPGA. In both cases reliable results are obtained quickly and conveniently, even for the case of a 300x300 nodes maze.

scholarly journals Producing Random Bits with Delay-Line-Based Ring Oscillators

2013 ◽  
Vol 59 (1) ◽  
pp. 41-50 ◽  
Author(s):  
Mieczysław Jessa ◽  
Łukasz Matuszewski
Keyword(s):  
High Frequency ◽  
Field Programmable Gate Array ◽  
Delay Line ◽  
Statistical Tests ◽  
Ring Oscillators ◽  
Delay Element ◽  
Novel Approach ◽  
Field Programmable ◽  
Cryptographic Attacks ◽  
Delay Elements

Abstract One of the sources of randomness for a random bit generator (RBG) is jitter present in rectangular signals produced by ring oscillators (ROs). This paper presents a novel approach for the design of delays used in these oscillators. We suggest using delay elements made on carry4 primitives instead of series of inverters or latches considered in the literature. It enables the construction of many high frequency ring oscillators with different nominal frequencies in the same field programmable gate array (FPGA). To assess the unpredictability of bits produced by RO-based RBG, the restarts mechanism, proposed in earlier papers, was used. The output sequences pass all NIST 800-22 statistical tests for smaller number of ring oscillators than the constructions described in the literature. Due to the number of ROs with different nominal frequencies and the method of construction of carry4 primitives, it is expected that the proposed RBG is more robust to cryptographic attacks than RBGs using inverters or latches as delay element.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array

Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Gamma Ray ◽  
Time Signal ◽  
Gamma Ray Spectrometer ◽  
Field Programmable ◽  
Gate Array ◽  
Real Time Signal Processing
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