scholarly journals Non-Volatile Transistor Memory with a Polypeptide Dielectric

Molecules ◽  
2020 ◽  
Vol 25 (3) ◽  
pp. 499 ◽  
Author(s):  
Lijuan Liang ◽  
Wenjuan He ◽  
Rong Cao ◽  
Xianfu Wei ◽  
Sei Uemura ◽  
...  
Keyword(s):  
Crystal Structure ◽  
Nonvolatile Memory ◽  
Solution Process ◽  
Molecular Alignment ◽  
Memory Window ◽  
Electrical Performance ◽  
Device Performance ◽  
Blend Ratio ◽  
Remarkable Increase ◽  
Synthetic Polypeptide

Organic nonvolatile transistor memory with synthetic polypeptide derivatives as dielectric was fabricated by a solution process. When only poly (γ-benzyl-l-glutamate) (PBLG) was used as dielectric, the device did not show obvious hysteresis in transfer curves. However, PBLG blended with PMMA led to a remarkable increase in memory window up to 20 V. The device performance was observed to remarkably depend on the blend ratio. This study suggests the crystal structure and the molecular alignment significantly affect the electrical performance in transistor-type memory devices, thereby provides an alternative to prepare nonvolatile memory with polymer dielectrics.

scholarly journals NaI Doping Effect on Photophysical Properties of Organic-Lead-Halide Perovskite Thin Films by Using Solution Process

2019 ◽  
Vol 2019 ◽  
pp. 1-9 ◽  
Author(s):  
Chuangchuang Chang ◽  
Xiaoping Zou ◽  
Jin Cheng ◽  
Ying Yang ◽  
Yujun Yao ◽  
...  
Keyword(s):  
Photophysical Properties ◽  
Perovskite Solar Cells ◽  
Solution Process ◽  
Precursor Solution ◽  
Critical Issue ◽  
Peak Position ◽  
Semiconductor Film ◽  
Device Performance ◽  
Perovskite Layer ◽  
Organic Lead

Perovskite solar cells (PSCs) have been developed rapidly in recent years. How to modify the photophysical properties of perovskite films has become the critical issue, affecting device performance. In this paper, NaI doping into the perovskite layer is attempted to modulate the photophysical properties to improve the performance of PSCs. The perovskite layer was prepared by using the one-step solution spin coating method with doping different concentrations of NaI into the perovskite precursor solution and chlorobenzene employed as the antisolvent. Experimental results show that the absorption band edge and the peak position of the PL spectrum of the doped perovskite thin film were red shifted; thus, the band gap of the semiconductor film became narrow. Doping NaI into perovskite is an effective way, by which the photophysical properties of perovskite films are well modified, thus improving device performance.

Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance

2011 ◽  
Vol 181-182 ◽  
pp. 307-311
Author(s):  
Hong Hanh Nguyen ◽  
Ngoc Son Dang ◽  
Van Duy Nguyen ◽  
Kyungsoo Jang ◽  
Kyunghyun Baek ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Nonvolatile Memory ◽  
Memory Performance ◽  
Charge Trapping ◽  
Oxide Thickness ◽  
Memory Window ◽  
Charge Storage ◽  
Operating Voltage ◽  
Silicon Clusters ◽  
Retention Characteristics

Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

Silicon Nanocrystalline Nonvolatile Memory - Characterization and Analysis

2016 ◽  
Vol 39 ◽  
pp. 134-150
Author(s):  
Valerii Ievtukh ◽  
A. Nazarov
Keyword(s):  
Nonvolatile Memory ◽  
Silicon Nanocrystals ◽  
Memory Window ◽  
Experimental Results ◽  
Memory Devices ◽  
Mos Capacitor ◽  
Mos Structure ◽  
Capacitance Voltage ◽  
Nonvolatile Memory Devices ◽  
Bipolar Memory

In this work, nanocrystal nonvolatile memory devices comprising of silicon nanocrystals located in gate oxide of MOS structure, were comprehensively studied on specialized modular data acquisition setup developed for capacitance-voltage measurements. The memory window formation, memory window retention and charge relaxation experimental methods were used to study the trapping/emission processes inside the dielectric layer of MOS capacitor memory. The trapping/emission processes were studied in standard bipolar memory mode and in new unipolar memory mode, which is specific for nanocrystalline nonvolatile memory. The analysis of experimental results shown that unipolar programming mode is more favourable for nanocrystalline memory operation due to lower wearing out and higher breakdown immunity of the MOS device’s oxide. The study was performed for two types of nanocrystalline memory devices: with one and two silicon nanocrystalline 2D layers in oxide of MOS structure correspondingly. The electrostatic modelling was presented to explain the experimental results.

Effect of TSV Joule Heating on Device Performance

2013 ◽  
Author(s):  
Fahad Mirza ◽  
Gaurang Naware ◽  
Thiagarajan Raman ◽  
Ankur Jain ◽  
Dereje Agonafer
Keyword(s):  
Joule Heating ◽  
Heat Dissipation ◽  
Form Factors ◽  
Signal Propagation ◽  
Junction Temperature ◽  
Electrical Performance ◽  
Device Performance ◽  
Base Line ◽  
Heat Current ◽  
Current Path

Convergence and miniaturization of consumer electronic products such as cameras, phones, etc. has been driven by enhanced performance and reduced microelectronics size. For past few decades Moore’s law has been driving the microelectronics industry to achieve high performance with small form-factors at a reasonable cost. While the continued miniaturization of the transistors has resulted in unparalleled growth of the electronics industry, further performance increment via size scaling could be cost-ineffective and difficult to manufacture. To satisfy the current/future integrated Circuit (IC) package requirements, vertical integration of chips holds the key, i.e., 3-D packaging. Chip-stacking (3-D) is emerging as a powerful technology to reduce package footprint, decrease interconnection power, higher frequencies, and provide efficient integration of heterogeneous devices. It allows further reduction in the form factor of current systems and eases the interconnect performance limitation since the components are integrated on top of each other instead of side-by-side, resulting in shorter interconnect lengths. Due to high package density and chip-stacking on top of each other, heat dissipation from the stacked chips becomes a concern. To overcome these thermal challenges and provide shorter/faster inter-chip electrical connection, Through Silicon Via (TSV) technology is being implemented in 3-D ICs. TSVs allow 3-D chips to be interconnected directly and provide high speed signal propagation. TSVs provide inter-chip heat/current path but the current flowing through the TSVs results in localized heat generation (Joule Heating) within the silicon, which could be detrimental to the overall performance of the system. In this paper, the effect of Joule heating on the device performance measured by trans-conductance, electron mobility (e− mobility), and channel thermal noise is analyzed. Thinned (100 μm) chips with a uniform power map and evenly distributed TSVs are analyzed in this work. Thermal distribution in the package is studied for different TSV currents including a base-line case of no-current (thermal TSV only) and the junction temperature is determined for each case. The response from the thermal analysis is correlated to the device performance through existing relations. Results indicate that joule heating has a significant effect on the thermal response of the 3D IC and subsequently proves to be detrimental to the chip performance. An understanding of the electrical performance dependence on TSV joule heating is developed through this work.

A double B←N bridged bipyridine (BNBP)-based polymer electron acceptor: all-polymer solar cells with a high donor : acceptor blend ratio

2017 ◽  
Vol 1 (5) ◽  
pp. 852-858 ◽  
Author(s):  
Xiaojing Long ◽  
Zicheng Ding ◽  
Chuandong Dou ◽  
Jun Liu ◽  
Lixiang Wang
Keyword(s):  
Solar Cells ◽  
Electron Donor ◽  
Electron Acceptor ◽  
Polymer Solar Cells ◽  
Device Performance ◽  
Blend Ratio ◽  
Donor Acceptor ◽  
Blend Ratios ◽  
High Donor

All-polymer solar cells with P3HT as an electron donor exhibit good device performance with high donor : acceptor blend ratios (w : w, from 0.5 : 1 to 9 : 1).

scholarly journals Influence of Carbon Quantum Dots on the Electrical Performance of Triboelectric Generators

Proceedings ◽  
2018 ◽  
Vol 2 (13) ◽  
pp. 1025 ◽  
Author(s):  
Vasiliki Prifti ◽  
Antigoni Siaraka ◽  
Aikaterini Giannouli ◽  
Apostolos Segkos ◽  
Achilleas Bardakas ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Quantum Dots ◽  
Film Thickness ◽  
Potential Application ◽  
Dielectric Film ◽  
Sliding Mode ◽  
Flexible Substrate ◽  
Carbon Quantum Dots ◽  
Electrical Performance ◽  
Device Performance

In this work we investigate the triboelectric properties of Carbon Quantum Dots (CQDs) films for potential application in triboelectric generators. CQDs were deposited on silicon wafers, using spin on techniques. Device performance was estimated in sliding mode experiments, where the CQDs-surface was sliding on top of a flexible substrate. The triboelectric signal as well as the charging of capacitors, after signal rectification, was monitored as a function of time. Our results indicate that surface roughness plays a very important role in the triboelectric signal and could compensate opposite trends due to other parameters, such as the dielectric film thickness.

Effects of Double Active Layer and Acetic Acid Stabilizer on the Electrical Properties of a Solution-Processed Zinc Tin Oxide Thin-Film Transistor

2015 ◽  
Vol 15 (10) ◽  
pp. 7743-7747 ◽  
Author(s):  
Ji Hun Shin ◽  
Sang Jo Kim ◽  
Seung Soo Ha ◽  
Yong Jin Im ◽  
Chan Hee Park ◽  
...  
Keyword(s):  
Thin Film ◽  
Acetic Acid ◽  
Active Layer ◽  
Tin Oxide ◽  
Solution Process ◽  
Oxide Thin Film ◽  
Electrical Performance ◽  
Hydroxyl Groups ◽  
Zinc Tin Oxide

We investigated the effects of a double active layer (DAL) and acetic acid stabilizer on zinc tin oxide (ZTO) thin-film transistors (TFTs) fabricated using a solution process. The DAL was composed of two layers created by a ZTO solution doped with the same or different percentiles of an atomic Sn concentration (30 at.%, 60 at.%). The electrical performance of the ZTO TFTs significantly was improved after we added acetic acid (AA) instead of monoethanolamine (MEA). This was accomplished by applying a type 2 DAL (bottom layer: Sn 60 at.%, top layer: Sn 30 at.%, 60/30) instead of other types (30/30 or 60/60). It was demonstrated that AA plays a role in lowering the decomposition temperature, enhancing the metal-oxygen bridge, and decreasing hydroxyl groups in the film. In addition, the type 2 DAL structure (60/30) lowered the Ioff of the ZTO TFT and controlled the carrier concentration in the channel. The best performances were obtained at a Sn concentration of 60 at.% in the bottom ZTO layer and 30 at.% in the top ZTO layer, with AA added as a stabilizer. The ZTO TFT exhibited an on/off ratio of 1.1×109, a saturation mobility of 5.04 cm2/V·s, a subthreshold slope of 0.11 V/decade, and a threshold voltage of 1.6 V.

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