scholarly journals A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 372 ◽  
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Xiaowei Liu
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Multi Stage ◽  
Sigma Delta Adc

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

The Design of CIFF Structure Three-Order Switched-Capacitor Sigma-Delta Modulator

2012 ◽  
Vol 433-440 ◽  
pp. 5727-5732
Author(s):  
Jun Han ◽  
Wei Dong Wang
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Optimization Technique ◽  
Cmos Technology ◽  
Switched Capacitor ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Transconductance Amplifier ◽  
A Chain

This paper presents the design and implementation of a single-loop three-order switched-capacitor sigma-delta modulator(SDM) with a standard 0.18um CMOS technology. A current optimization technique is utilized in proposed design to reduce the power of operational transconductance amplifier(OTA).Using a chain of Integrators with weighted feed-forward summation(CIFF) structure and optimized single-stage class-A OTA with positive feed-back to minimize the power consumption. The SDM has been presented with an over-sampling ratio of 128,clock frequency 6.144MHz,24kHz band- width, and achieves a peak SNR of 100dB,103dB dynamic range. The whole circuits consume 2.87mW from a single 1.8V supply voltage.

A Fourth-Order MASH Sigma-Delta Modulator in Inertial Sensors

2013 ◽  
Vol 562-565 ◽  
pp. 311-316
Author(s):  
Xiao Wei Liu ◽  
Qiang Li ◽  
Guan Nan Sun ◽  
Wen Yan Liu
Keyword(s):  
Inertial Sensors ◽  
Signal To Noise Ratio ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Technical Requirements ◽  
System Level Simulation ◽  
Multi Stage ◽  
Multi Phase

The theory of a Sigma-Delta modulator is introduced in this paper. Based on this theory, a feedback 2-1-1 multi-stage-noise-shaping (MASH) sigma-delta modulator is designed, and the coefficients of the modulator are calculated. The system-level simulation results show that the effective number of bits (ENOB) is 24 bits when the signal bandwidth is 1 kHz and the over-sampling (OSR) rate is 128. Then the circuits of modulator are designed, including integrator, comparator, multi-phase clock and the noise cancelling logic. The whole modulator is simulated in Cadence, the signal to noise ratio (SNR) of the modulator is 125.4dB, and the ENOB is 21.1bits, which meet the technical requirements of the sensor.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

2013 ◽  
Vol 22 (09) ◽  
pp. 1340012
Author(s):  
KAREN WAN ◽  
GIGI CHAN ◽  
WILLIAM WONG ◽  
KAM CHUEN WAN ◽  
BRYCE YAU ◽  
...  
Keyword(s):  
Fourth Order ◽  
Cmos Technology ◽  
Second Order ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital Conversion ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Analog To Digital Conversion

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

scholarly journals A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Chi Xu ◽  
Yu Jin ◽  
Duli Yu
Keyword(s):  
Fractional Order ◽  
Analog Circuit ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Integer Order ◽  
Noise Characteristics ◽  
Chip Testing ◽  
Sigma Delta Adc

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

A 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope

2015 ◽  
Vol 645-646 ◽  
pp. 605-609
Author(s):  
Ying Kai Zhao ◽  
Liang Yin ◽  
Zhao Tong Liu ◽  
Wei Ping Chen ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Digital To Analog Converter ◽  
Sigma Delta ◽  
Interpolation Filter ◽  
Reconstruction Filter ◽  
The Stability ◽  
Fifth Order

In this paper, a 16 Bits 500 kHz Sigma-Delta DAC for Silicon Micro Gyroscope is proposedin order to enhance the precision of the digital to analog converter level.The interpolation filterhas achieved 64 times interpolation function,using three cascaded manner, it employs three level cascaded of FIR filterstructure. It achieves a 64 times oversampling feature. The signalbandwidth of the designs interpolation filter is 100 kHz, SNR reach 106dB. Fifth-order single-loop structure CIFB achieve noise shaping modulator function to verify the stability of the system, after the completion of CSD coefficient coding, signal to noise ratio reached 119.7dB, effective bits reached 19.59. The switched capacitor technology actualize analog reconstruction filter module, and using a typically switched capacitor DAC achieved high jump "0, 1" digital signal is converted into an analog signal, the digital-analog conversion achieved.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

A 16 Bits Sigma-Delta Modulator Applied in Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1077-1081
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Ying Kai Zhao ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Cmos Process ◽  
Noise Shaping ◽  
Effective Number ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Multi Stage ◽  
Ideal Situation ◽  
Sample Frequency ◽  
Sigma Delta Adc ◽  
The Ideal

In this paper, a 4th-order sigma-delta modulator applied in gyroscope is presented. This modulator adopts the 2-1-1 Multi stage noise shaping structure. The bandwidth of signal is 100 KHz, the over sample rate is 64, and sample frequency is 12.8MHz. By the MATLAB Simulink modeling and simulation, when the input signal is 100 KHz, the SNDR of the MASH ADC is 121.8dB, and the effective number of bit is 19.93 in ideal situation. After considering non-ideal factors, the SNDR is 111.6dB, the effective number of bit of ADC is 18.28. Compared with the ideal situation, the noise floor of PSD has increased 40dB. It explains that non-ideal factors have a significant effect on the performance of the sigma-delta ADC. The 4th-order MASH sigma-delta modulator has been implemented under 0.5 um CMOS process and simulated under Cadence. The final simulation results show that SNDR is 112.4 dB and effective number of bits (ENOB) is 18.6.

scholarly journals Ab initiostructure determination of nanocrystals of organic pharmaceutical compounds by electron diffraction at room temperature using a Timepix quantum area direct electron detector

2016 ◽  
Vol 72 (2) ◽  
pp. 236-242 ◽  
Author(s):  
E. van Genderen ◽  
M. T. B. Clabbers ◽  
P. P. Das ◽  
A. Stewart ◽  
I. Nederlof ◽  
...  
Keyword(s):  
Electron Diffraction ◽  
Room Temperature ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Three Dimensional ◽  
Direct Methods ◽  
Liquid Nitrogen Temperature ◽  
High Dynamic Range ◽  
Electron Diffraction Data ◽  
High Signal

Until recently, structure determination by transmission electron microscopy of beam-sensitive three-dimensional nanocrystals required electron diffraction tomography data collection at liquid-nitrogen temperature, in order to reduce radiation damage. Here it is shown that the novel Timepix detector combines a high dynamic range with a very high signal-to-noise ratio and single-electron sensitivity, enablingab initiophasing of beam-sensitive organic compounds. Low-dose electron diffraction data (∼0.013 e− Å−2 s−1) were collected at room temperature with the rotation method. It was ascertained that the data were of sufficient quality for structure solution using direct methods using software developed for X-ray crystallography (XDS,SHELX) and for electron crystallography (ADT3D/PETS,SIR2014).

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