scholarly journals Hysteresis in As-Synthesized MoS2 Transistors: Origin and Sensing Perspectives

Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 646
Author(s):  
Carlos Marquez ◽  
Norberto Salazar ◽  
Farzan Gity ◽  
Jose C. Galdon ◽  
Carlos Navarro ◽  
...  
Keyword(s):  
Hexagonal Boron Nitride ◽  
Pressure Sensors ◽  
Drain Current ◽  
Thin Layers ◽  
Gate Insulator ◽  
Sensor Performance ◽  
Electrical Hysteresis ◽  
Device Reliability ◽  
Extreme Sensitivity ◽  
Reliability Issue

Two-dimensional materials, including molybdenum disulfide (MoS2), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials still exhibit integration difficulties with complementary-MOS standardized processes and methods. The device reliability is compromised by gate insulator selection and the quality of the metal/semiconductor and semiconductor/insulator interfaces. Despite some improvements regarding mobility, hysteresis and Schottky barriers having been reported thanks to metal engineering, vertically stacked heterostructures with compatible thin-layers (such as hexagonal boron nitride or device encapsulation) variability is still an important constraint to sensor performance. In this work, we fabricated and extensively characterized the reliability of as-synthesized back-gated MoS2 transistors. Under atmospheric and room-temperature conditions, these devices present a wide electrical hysteresis (up to 5 volts) in their transfer characteristics. However, their performance is highly influenced by the temperature, light and pressure conditions. The singular signature in the time response of the devices points to adsorbates and contaminants inducing mobile charges and trapping/detrapping carrier phenomena as the mechanisms responsible for time-dependent current degradation. Far from being only a reliability issue, we demonstrated a method to exploit this device response to perform light, temperature and/or pressure sensors in as-synthesized devices. Two orders of magnitude drain current level differences were demonstrated by comparing device operation under light and dark conditions while a factor up to 105 is observed at vacuum versus atmospheric pressure environments.

Wide range modulation of synaptic weight in thin-film transistors with hafnium oxide gate insulator and indium-zinc oxide channel layer for artificial synapse application

Nanoscale ◽  
2021 ◽  
Author(s):  
Keonwon Beom ◽  
Jimin Han ◽  
Hyun-Mi Kim ◽  
Tae-Sik Yoon
Keyword(s):  
Thin Film ◽  
Zinc Oxide ◽  
Thin Film Transistors ◽  
Hafnium Oxide ◽  
Synaptic Weight ◽  
Drain Current ◽  
Gate Insulator ◽  
Channel Layer ◽  
Indium Zinc Oxide ◽  
Wide Range

Wide range synaptic weight modulation with a tunable drain current was demonstrated in thin-film transistors (TFTs) with a hafnium oxide (HfO2−x) gate insulator and an indium-zinc oxide (IZO) channel layer...

Study of Transport Through Low-Temperature GaAs Surface Insulator Layers

1991 ◽  
Vol 241 ◽  
Author(s):  
J. P. Ibbetson ◽  
L.-W. Yin ◽  
M. Hashemi ◽  
A. C. Gossard ◽  
U. K. Mishra
Keyword(s):  
Material Properties ◽  
Surface Effect ◽  
Thin Layers ◽  
Gate Insulator ◽  
High Resistivity ◽  
Growth Surface ◽  
Insulator Layer ◽  
Insulator Layers ◽  
Low Temperature Gaas ◽  
Effective Buffer

ABSTRACTSince epilayers of GaAs grown at low substrate temperature (LTGaAs) and annealed at 600°C were first demonstrated to be an effective buffer layer for eliminating backgating effects, the material properties and electronic characteristics of bulk LTGaAs have been actively investigated. Less attention has been paid to thin layers of LTGaAs (∼2000Å), although these have been shown to improve gate-to-drain breakdown characteristics when incorporated as the surface insulator layer in GaAs MISFET's. In bulk LTGaAs that has been annealed for 10 minutes at 600°C, the formation of arsenic precipitates with a density of 1018 cm-3 has been observed. These are considered to be at least partially responsible for the high resistivity of LTGaAs2. While the exact mechanism of precipitate formation is currently unknown, it would seem reasonable to expect the availability of the growth surface to have a significant effect on any defect redistribution during the anneal. This surface effect would become increasingly apparent as the LTGaAs layer thickness was decreased. It is desirable for MISFET applications that the LTGaAs gate insulator layer be as thin as possible, whilst maintaining high breakdown, in order to maximize device transconductance. To achieve this, it is important to understand how the observed bulk features (such as ∼60Å size arsenic precipitates) are affected in thin LTGaAs layers

scholarly journals Channel temperature analysis of AlGaN/GaN HEMTs in quasi-static and pulse operation mode

2018 ◽  
Vol 69 (5) ◽  
pp. 390-394
Author(s):  
Martin Florovič ◽  
Róbert Szobolovszký ◽  
Jaroslav Kováč ◽  
Jaroslav Kováč ◽  
Aleš Chvála ◽  
...  
Keyword(s):  
Operation Mode ◽  
Drain Current ◽  
Temperature Dependent ◽  
Saturation Velocity ◽  
Channel Temperature ◽  
Device Reliability ◽  
Source Resistance ◽  
Current Change ◽  
Voltage Saturation

Abstract GaN-based HEMTs’ high potential is deteriorated by self-heating during the operation, this has influence on the electrical properties as well as device reliability. This work is focused on an average channel temperature determination of power AlGaN/GaN HEMT prepared on SiC substrate using quasi-static and pulsed I-V characterization. There was analyzed the drain current change relation to temperature dependent electrical HEMT parameters such as source resistance, threshold voltage, saturation velocity, resp. leakage current which allows to calculate an average channel temperature versus dissipated power for various ambient temperature. Differential temperature of investigated device with and without heatsink was determined. Obtained results were discussed using simulated spatial temperature distribution.

High Voltage AlGaN/GaN Heterojunction Transistors

2004 ◽  
Vol 14 (01) ◽  
pp. 225-243 ◽  
Author(s):  
L. S. McCarthy ◽  
N-Q. Zhang ◽  
H. Xing ◽  
B. Moran ◽  
S. DenBaars ◽  
...  
Keyword(s):  
Drain Current ◽  
Gate Insulator ◽  
Threading Dislocation ◽  
High Electron ◽  
Resistive Load ◽  
Power Switching ◽  
Field Plate ◽  
Switching Power ◽  
Dislocation Densities ◽  
Extrinsic Base

The use of AlGaN / GaN HEMTs and HBTs for switching power supplies is explored. With its high electron velocities and breakdown fields, GaN has great potential for power switching. The field-plate HEMT increased breakdown voltages by 20% to 570V by reducing the peak field at the drain-side edge of the gate. The use of a gate insulator is also investigated, using both JVD SiO 2 and e-beam evaporated SiO 2 to reduce gate leakage, increasing breakdown voltages to 1050V and 1300V respectively. The power device figure of merit (FOM) for these devices: [Formula: see text], is the highest reported for switching devices. To reduce trapping effects, reactively sputtered SiN x, is used as a passivant, resulting in a switching time of less than 30 ns for devices blocking over 110V with a drain current of 1.4A under resistive load conditions. Dynamic load results are also presented. The development of HBTs for switching applications included the development of an etched emitter HBT with a selectively regrown extrinsic base. This was later improved upon with the selectively regrown emitter devices with current gains as high as 15. To improve breakdown in these devices, thick GaN layers were grown, reducing threading dislocation densities in the active layers. A further improvement included the use of a bevelled shallow etch and a lateral collector design to maximize device breakdown.

Linearity Analysis of GME-TRC MOSFET Using SiO2 as a Gate Insulator at High Temperature

2013 ◽  
Vol 685 ◽  
pp. 207-210
Author(s):  
Priyanka Malik ◽  
R.S. Gupta ◽  
Mridula Gupta
Keyword(s):  
Drain Current ◽  
Paper Analysis ◽  
Performance Comparison ◽  
Gate Insulator ◽  
Third Order ◽  
Temperature Variations ◽  
Analog Performance ◽  
Recessed Channel ◽  
Bias Point ◽  
The Impact

This paper analysis the impact of temperature variation on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET and trapezoidal recessed channel (TRC) MOSFET, using ATLAS: 3D device simulator [. The study focuses on the linearity and analog performance comparison of GME-TRC and TRC MOSFETs and the impact of temperature variations on some of the key parameters like drain current, transconductance and the optimum bias point in terms of gm3 (third order derivative of Ids-Vgs) and VIP3 has been analysed.

EFFECT OF GATE INSULATOR ON THE PERFORMANCE OF COPPER PHTHALOCYANINE-BASED ORGANIC THIN FILM TRANSISTORS

2011 ◽  
Vol 10 (04n05) ◽  
pp. 745-748
Author(s):  
N. PADMA ◽  
SHASWATI SEN ◽  
A. K. CHAUHAN ◽  
D. K. ASWAL ◽  
S. K. GUPTA ◽  
...  
Keyword(s):  
Dielectric Constant ◽  
Field Effect ◽  
Gate Dielectric ◽  
Copper Phthalocyanine ◽  
Field Effect Transistors ◽  
Drain Current ◽  
Dielectric Constants ◽  
Gate Insulator ◽  
Operating Voltage ◽  
Organic Thin Film

Effect of the gate dielectric on the performance of Copper phthalocyanine (CuPc) based top contact organic field effect transistors (OFET) has been studied using thermally grown SiO2 and sputtered HfO x films with dielectric constants of 3.9 and 12.5 respectively. Operating voltages of the devices on SiO2 and HfO x were found to be 10–50 V and 2–3 V, respectively. The lower operating voltage for HfO x is attributed to the higher dielectric constant. Devices on SiO2 and HfO x were found to have field effect mobilities of 0.01 and 3.5 × 10-3 cm2/Vs and drain current modulation of 103 and 102, respectively. Scanning Electron Microscopy showed widely scattered nanowires on HfO x and densely packed nanofibers on SiO2 . X-ray diffraction studies showed better crystallinity of films on SiO2 . The results show that operating voltage of devices can be reduced by using higher dielectric constant material while mobility and FET characteristics depend on structure of CuPc that in turn is influenced by the dielectric.

Characteristics of Gamma–Ray Irradiated Pentacene Organic Thin Film Field Effect Transistors

2011 ◽  
Vol 306-307 ◽  
pp. 185-192 ◽  
Author(s):  
Hiroaki Yano ◽  
Li Cai ◽  
Toshio Hirao ◽  
Zong Fan Duan ◽  
Yutaro Takayanagi ◽  
...  
Keyword(s):  
Field Effect ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Uv Light ◽  
Drain Current ◽  
Gate Insulator ◽  
Organic Thin Film ◽  
Drain Voltage ◽  
Continuous Increase ◽  
Uv Light Irradiation

P-channel pentacene field effect transistorswith a Si/SiO2/pentacene/Au structure were fabricated, and were gamma-ray irradiated with a Co60source. The changes of the drain current IDvs. source/drain voltage VSD(ID- VSD) characteristics were measured after every 200 Gy in silicon (GySi) irradiations up to the total dose of 1200 GySi. The drain current IDcontinuously decreased to less than 10 % of that before irradiation after 1200 GySiirradiation. The threshold voltage Vthcontinuously decreased up to 800 GySi, started to saturate above 800 GySi,and recovered above1000 GySi. The mobility m continued to decrease up to 1200 GySi. Those behaviors were explained by accumulation of positive trapped charge within the gate insulator SiO2near the interface, continuous increase of interface traps near the interface between the SiO2and pentacene, and build up of electrons in the channel regions. These behaviors were discussed in comparisons with previously reported results on ultraviolet (UV) light irradiation experiments on similarly structured pentacene-based transistors.

Fabrication of Transparent Ferroelectric-Gate Thin Film Transistors with Nonvolatile Memory Operation

2005 ◽  
Vol 902 ◽  
Author(s):  
Eisuke Tokumitsu ◽  
Masaru Senoo ◽  
Etsu Shin
Keyword(s):  
Thin Film ◽  
Indium Tin Oxide ◽  
Gate Voltage ◽  
Thin Film Transistors ◽  
Nonvolatile Memory ◽  
Quartz Substrate ◽  
Drain Current ◽  
Optical Transmittance ◽  
Gate Insulator ◽  
Current Drain

AbstractWe demonstrate transparent thin film transistors (TFTs) with nonvolatile memory operation using Bi4-xLaxTi3O12 (BLT) as a gate insulator and indium tin oxide (ITO) as a channel. ITO is also used for the gate, source and drain electrodes. Drain current-drain voltage (ID-VD) characteristics of transparent ITO/BLT ferroelectric-gate TFTs exhibit excellent n-channel transistor operations. On current of 0.35 mA was obtained when the applied gate voltage is 6V. On the other hand, the off current of the device is as low as 10-10A, which indicates that the ITO channel is sufficiently depleted by the ferroelectric polarization. In addition, drain current-gate voltage (ID-VG) characteristics demonstrate clear counterclockwise hysteresis loop due to the ferroelectric gate insulator. Optical transmittance of the fabricated device is greater than 60% including the quartz substrate.

Off-state drain current and breakdown voltage of AlGaN/GaN MIS-HEMT with multilayered gate insulator

2007 ◽  
Vol 4 (7) ◽  
pp. 2682-2685 ◽  
Author(s):  
S. Yagi ◽  
M. Shimizu ◽  
M. Inada ◽  
H. Okumura ◽  
H. Ohashi ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
Drain Current ◽  
Gate Insulator

Fabrication and Characterization of 4H-SiC MOSFET with MOCVD-Grown Al2O3 Gate Insulator

2007 ◽  
Vol 556-557 ◽  
pp. 787-790 ◽  
Author(s):  
Shiro Hino ◽  
Tomohiro Hatayama ◽  
Naruhisa Miura ◽  
Tatsuo Oomori ◽  
Eisuke Tokumitsu
Keyword(s):  
Photoelectron Spectroscopy ◽  
Chemical Vapor ◽  
Drain Current ◽  
Interface State ◽  
State Density ◽  
Gate Insulator ◽  
Organic Chemical ◽  
Mos Capacitors ◽  
Significant Difference ◽  
Metal Organic

We have fabricated and characterized MOS capacitors and lateral MOSFETs using Al2O3 as a gate insulator. Al2O3 films were deposited by metal-organic chemical vapor deposition (MOCVD) at temperatures as low as 190 oC using tri-ethyl-aluminum and H2O as precursors. We first demonstrate from the capacitance – voltage (C-V) measurements that the Al2O3/SiC interface has lower interface state density than the thermally-grown SiO2/SiC interface. No significant difference was observed between X-ray photoelectron spectroscopy (XPS) Si 2p spectrum from the Al2O3/SiC interface and that from the SiC substrate, which means the SiC substrate was not oxidized during the Al2O3 deposition. Next, we show that the fabricated lateral SiC-MOSFETs with Al2O3 gate insulator have good drain current – drain voltage (ID-VD) and drain current – gate voltage (ID-VG) characteristics with normally-off behavior. The obtained peak values of field-effect mobility (μFE) are between 68 and 88 cm2/Vs.

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