scholarly journals Unidirectional Operation of p-GaN Gate AlGaN/GaN Heterojunction FET Using Rectifying Drain Electrode

Micromachines ◽  
2021 ◽  
Vol 12 (3) ◽  
pp. 291
Author(s):  
Tae-Hyeon Kim ◽  
Won-Ho Jang ◽  
Jun-Hyeok Yim ◽  
Ho-Young Cha
Keyword(s):  
Computer Aided Design ◽  
Process Step ◽  
Maximum Current ◽  
Blocking Device ◽  
Drain Electrode ◽  
Additional Process ◽  
Effect Transistor ◽  
Tcad Simulation ◽  
Switching Characteristics ◽  
Aided Design

In this study, we proposed a rectifying drain electrode that was embedded in a p-GaN gate AlGaN/GaN heterojunction field-effect transistor to achieve the unidirectional switching characteristics, without the need for a separate reverse blocking device or an additional process step. The rectifying drain electrode was implemented while using an embedded p-GaN gating electrode that was placed in front of the ohmic drain electrode. The embedded p-GaN gating electrode and the ohmic drain electrode are electrically shorted to each other. The concept was validated by technology computer aided design (TCAD) simulation along with an equivalent circuit, and the proposed device was demonstrated experimentally. The fabricated device exhibited the unidirectional characteristics successfully, with a threshold voltage of ~2 V, a maximum current density of ~100 mA/mm, and a forward drain turn-on voltage of ~2 V.

scholarly journals Demonstration of Fin-Tunnel Field-Effect Transistor with Elevated Drain

Micromachines ◽  
2019 ◽  
Vol 10 (1) ◽  
pp. 30 ◽  
Author(s):  
Jang Hyun Kim ◽  
Hyun Woo Kim ◽  
Garam Kim ◽  
Sangwan Kim ◽  
Byung-Gook Park
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Electrical Performance ◽  
Control Group ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
High Level ◽  
Aided Design

In this paper, a novel tunnel field-effect transistor (TFET) has been demonstrated. The proposed TFET features a SiGe channel, a fin structure and an elevated drain to improve its electrical performance. As a result, it shows high-level ON-state current (ION) and low-level OFF-state current (IOFF); ambipolar current (IAMB). In detail, its ION is enhanced by 24 times more than that of Si control group and by 6 times more than of SiGe control group. The IAMB can be reduced by up to 900 times compared with the SiGe control group. In addition, technology computer-aided design (TCAD) simulation is performed to optimize electrical performance. Then, the benchmarking of ON/OFF current is also discussed with other research group’s results.

scholarly journals 4H-SiC Double-Trench MOSFET with Side Wall Heterojunction Diode for Enhanced Reverse Recovery Performance

Energies ◽  
2020 ◽  
Vol 13 (18) ◽  
pp. 4602
Author(s):  
Junghun Kim ◽  
Kwangsoo Kim
Keyword(s):  
Computer Aided Design ◽  
Side Wall ◽  
Oxide Semiconductor ◽  
Heterojunction Diode ◽  
Power Module ◽  
Switching Performance ◽  
Conduction State ◽  
Effect Transistor ◽  
Switching Characteristics ◽  
Aided Design

In this study, a novel 4H-SiC double-trench metal-oxide semiconductor field-effect transistor (MOSFET) with a side wall heterojunction diode is proposed and investigated by conducting numerical technology computer-aided design simulations. The junction between P+ polysilicon and the N-drift layer forming a heterojunction diode on the side wall of the source trench region suppresses the operation of the PiN body diode during the reverse conduction state. Therefore, the injected minority carriers are completely suppressed, reducing the reverse recovery current by 73%, compared to the PiN body diodes. The switching characteristics of the proposed MOSFET using the heterojunction diode as a freewheeling diode was compared to the power module with a conventional MOSFET and an external diode as a freewheeling diode. It is shown that the switching performance of the proposed structure exhibits equivalent characteristics compared to the power module, enabling the elimination of an external freewheeling diode in the power system.

Analysis of Channel Area Fluctuation Effects of Gate-All-Around Tunnel Field-Effect Transistor

2020 ◽  
Vol 20 (7) ◽  
pp. 4409-4413
Author(s):  
Seok Jung Kang ◽  
Jeong-Uk Park ◽  
Kyung Jin Rim ◽  
Yoon Kim ◽  
Jang Hyun Kim ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Oxide Semiconductor ◽  
Fluctuation Effects ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Tcad Simulation ◽  
Aided Design ◽  
First Time

In this manuscript, channel area fluctuation (CAF) effects on turn-on voltage (Von) and subthreshold swing (SS) in gate-all-around (GAA) nanowire (NW) tunnel field-effect transistor (TFET) with multi-bridge-channel (MBC) have been investigated for the first time. These variations occur because oblique etching slope makes various elliptical-shaped channels in MBC-TFET. Since TFET is promising candidates to succeed metal-oxide-semiconductor FETs (MOSFET), these variation effects have been compared to MOSFET. Furthermore, Ge homojunction TFET, one of the solutions to increase on-state current in TFET and improve SS also has been simulated using technology computer-aided design (TCAD) simulation. The results would be worth reference for future study about GAA NW TFETs.

scholarly journals Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

2021 ◽  
Vol 11 (24) ◽  
pp. 12075
Author(s):  
Jee-Hun Jeong ◽  
Ogyun Seok ◽  
Ho-Jun Lee
Keyword(s):  
Analytical Model ◽  
Computer Aided Design ◽  
Analytical Modeling ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Electrical Characteristics ◽  
Reverse Transfer ◽  
Tcad Simulation ◽  
Switching Characteristics ◽  
Aided Design

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

TCAD Study of the Raised SiGe Source/Drain in 40nm PMOS

2015 ◽  
Vol 645-646 ◽  
pp. 70-74 ◽  
Author(s):  
Min Zhong ◽  
Yu Hang Zhao ◽  
Shou Mian Chen ◽  
Ming Li ◽  
Shao Hai Zeng ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Critical Role ◽  
Sige Layer ◽  
Strain Engineering ◽  
Effect Transistor ◽  
Simulation Results ◽  
Aided Design ◽  
The Relationship ◽  
Growth Experiments ◽  
Good Agreement

An embedded SiGe layer was applied in the source/drain areas (S/D) of a field-effect transistor to boost the performance in the p channels. Raised SiGe S/D plays a critical role in strain engineering. In this study, the relationship between the SiGe overfilling and the enhancement of channel stress was investigated. Systematic technology computer aided design (TCAD) simulations of the SiGe overfill height in a 40 nm PMOS were performed. The simulation results indicate that a moderate SiGe overfilling induces the highest stress in the channel. Corresponding epitaxial growth experiments were done and the obtained experimental data was in good agreement with the simulation results. The effect of the SiGe overfilling is briefly discussed. The results and conclusions presented within this paper might serve as useful references for the optimization of the embedded SiGe stressor for 40 nm logic technology node and beyond.

Element Edge Based Discretization for TCAD Device Simulation

2021 ◽  
Author(s):  
Juan Sanchez ◽  
Qiusong Chen
Keyword(s):  
Computer Aided Design ◽  
Field Effect Transistor ◽  
Semiconductor Device ◽  
Device Simulation ◽  
Polarization Effects ◽  
Effect Transistor ◽  
Edge Based ◽  
Volume Method ◽  
Aided Design ◽  
Novel Devices

<div><div><div><p>Technology computer-aided design (TCAD) semiconductor device simulators solve partial differential equations (PDE) using the finite volume method (FVM), or related methods. While this approach has been in use over several decades, its methods continue to be extended, and are still applicable for investigating novel devices. In this paper, we present an element edge based (EEB) FVM discretization approach suitable for capturing vector-field effects. Drawing from a 2D approach in the literature, we have extended this method to 3D. We implemented this method in a TCAD semiconductor device simulator, which uses a generalized PDE (GPDE) approach to simulate de- vices with the FVM. We describe how our EEB method is compatible with the GPDE approach, allowing the modeling of vector effects using scripting. This method is applied to solve polarization effects in a 3D ferro capacitor, and a 2D ferroelectric field-effect transistor. An example for field- dependent mobility in a 3D MOSFET is also presented.</p></div></div></div>

scholarly journals Design and Optimization of Germanium-Based Gate-Metal-Core Vertical Nanowire Tunnel FET

Micromachines ◽  
2019 ◽  
Vol 10 (11) ◽  
pp. 749 ◽  
Author(s):  
Jang ◽  
Yoon ◽  
Cho ◽  
Jung ◽  
Lee ◽  
...  
Keyword(s):  
Computer Aided Design ◽  
Design Parameters ◽  
Channel Height ◽  
Logic Device ◽  
Metal Core ◽  
Design And Optimization ◽  
Channel Thickness ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Aided Design

In this paper, a germanium-based gate-metal-core vertical nanowire tunnel field effect transistor (VNWTFET) has been designed and optimized using the technology computer-aided design (TCAD) simulation. In the proposed structure, by locating the gate-metal as a core of the nanowire, a more extensive band-to-band tunneling (BTBT) area can be achieved compared with the conventional core–shell VNWTFETs. The channel thickness (Tch), the gate-metal height (Hg), and the channel height (Hch) were considered as the design parameters for the optimization of device performances. The designed gate-metal-core VNWTFET exhibits outstanding performance, with an on-state current (Ion) of 80.9 μA/μm, off-state current (Ioff) of 1.09 × 10−12 A/μm, threshold voltage (Vt) of 0.21 V, and subthreshold swing (SS) of 42.8 mV/dec. Therefore, the proposed device was demonstrated to be a promising logic device for low-power applications.

scholarly journals A New Read Scheme for Alleviating Cell-to-Cell Interference in Scaled-Down 3D NAND Flash Memory

Electronics ◽  
2020 ◽  
Vol 9 (11) ◽  
pp. 1775
Author(s):  
Jae-Min Sim ◽  
Myounggon Kang ◽  
Yun-Heub Song
Keyword(s):  
Electric Field ◽  
Flash Memory ◽  
Computer Aided Design ◽  
Fundamental Problem ◽  
Adjacent Cell ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Fundamental Cause ◽  
Tcad Simulation ◽  
Aided Design

In this paper, we investigated the cell-to-cell interference in scaled-down 3D NAND flash memory by using a Technology Computer-Aided Design (TCAD) simulation. The fundamental cause of cell-to-cell interference is that the electric field crowding point is changed by the programmed adjacent cell so that the electric field is not sufficiently directed to the channel surface. Therefore, the channel concentration of the selected cell is changed, leading to a Vth shift. Furthermore, this phenomenon occurs more severely when the selected cell is in an erased state rather than in a programmed state. In addition, it was confirmed that the cell-to-cell interference by the programmed WLn+1 is more severe than that of WLn−1 due to the degradation of the effective mobility effect. To solve this fundamental problem, a new read scheme is proposed. Through TCAD simulation, the cell-to-cell interference was alleviated with a bias having a ΔV of 1.5 V from Vread through an optimization process to have appropriate bias conditions in three ways that are suitable for each pattern. As a result, this scheme narrowed the Vth shift of 67.5% for erased cells and narrowed the Vth shift of 70% for programmed cells. The proposed scheme is one way to solve the cell-to-cell interference that may occur as the cell-to-cell distance decreases for a high stacked 3D NAND structure.

scholarly journals 3D AND-Type Stacked Array for Neuromorphic Systems

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 829
Author(s):  
Taejin Jang ◽  
Suhyeon Kim ◽  
Jeesoo Chang ◽  
Kyung Kyu Min ◽  
Sungmin Hwang ◽  
...  
Keyword(s):  
Flash Memory ◽  
Computer Aided Design ◽  
Power Level ◽  
Matrix Multiplication ◽  
Simple Program ◽  
Neuromorphic Systems ◽  
Tcad Simulation ◽  
Cell Variation ◽  
Aided Design ◽  
Implantation Method

NOR/AND flash memory was studied in neuromorphic systems to perform vector-by-matrix multiplication (VMM) by summing the current. Because the size of NOR/AND cells exceeds those of other memristor synaptic devices, we proposed a 3D AND-type stacked array to reduce the cell size. Through a tilted implantation method, the conformal sources and drains of each cell could be formed, with confirmation by a technology computer aided design (TCAD) simulation. In addition, the cell-to-cell variation due to the etch slope could be eliminated by controlling the deposition thickness of the cells. The suggested array can be beneficial in simple program/inhibit schemes given its use of Fowler–Nordheim (FN) tunneling because the drain lines and source lines are parallel. Therefore, the conductance of each synaptic device can be updated at low power level.

Sign in / Sign up

Export Citation Format

Share Document