scholarly journals A Scalable and Low Stress Post-CMOS Processing Technique for Implantable Microsensors

Micromachines ◽  
2020 ◽  
Vol 11 (10) ◽  
pp. 925
Author(s):  
Ah-Hyoung Lee ◽  
Jihun Lee ◽  
Farah Laiwalla ◽  
Vincent Leung ◽  
Jiannan Huang ◽  
...  
Keyword(s):  
Ex Vivo ◽  
Complementary Metal Oxide Semiconductor ◽  
Processing Technique ◽  
Oxide Semiconductor ◽  
Wireless Power ◽  
Post Processing ◽  
Sensors And Actuators ◽  
Data Link ◽  
Body Sensors ◽  
Cmos Processing

Implantable active electronic microchips are being developed as multinode in-body sensors and actuators. There is a need to develop high throughput microfabrication techniques applicable to complementary metal–oxide–semiconductor (CMOS)-based silicon electronics in order to process bare dies from a foundry to physiologically compatible implant ensembles. Post-processing of a miniature CMOS chip by usual methods is challenging as the typically sub-mm size small dies are hard to handle and not readily compatible with the standard microfabrication, e.g., photolithography. Here, we present a soft material-based, low chemical and mechanical stress, scalable microchip post-CMOS processing method that enables photolithography and electron-beam deposition on hundreds of micrometers scale dies. The technique builds on the use of a polydimethylsiloxane (PDMS) carrier substrate, in which the CMOS chips were embedded and precisely aligned, thereby enabling batch post-processing without complication from additional micromachining or chip treatments. We have demonstrated our technique with 650 μm × 650 μm and 280 μm × 280 μm chips, designed for electrophysiological neural recording and microstimulation implants by monolithic integration of patterned gold and PEDOT:PSS electrodes on the chips and assessed their electrical properties. The functionality of the post-processed chips was verified in saline, and ex vivo experiments using wireless power and data link, to demonstrate the recording and stimulation performance of the microscale electrode interfaces.

scholarly journals Imaging-based spectrometer-less optofluidic biosensors based on dielectric metasurfaces for detecting extracellular vesicles

2021 ◽  
Vol 12 (1) ◽  
Author(s):  
Yasaman Jahani ◽  
Eduardo R. Arvelo ◽  
Filiz Yesilkoy ◽  
Kirill Koshelev ◽  
Chiara Cianciaruso ◽  
...  
Keyword(s):  
Real Time ◽  
Extracellular Vesicles ◽  
Bound States ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Spectral Shift ◽  
Processing Technique ◽  
Oxide Semiconductor ◽  
Linear Estimator ◽  
Large Area

AbstractBiosensors are indispensable tools for public, global, and personalized healthcare as they provide tests that can be used from early disease detection and treatment monitoring to preventing pandemics. We introduce single-wavelength imaging biosensors capable of reconstructing spectral shift information induced by biomarkers dynamically using an advanced data processing technique based on an optimal linear estimator. Our method achieves superior sensitivity without wavelength scanning or spectroscopy instruments. We engineered diatomic dielectric metasurfaces supporting bound states in the continuum that allows high-quality resonances with accessible near-fields by in-plane symmetry breaking. The large-area metasurface chips are configured as microarrays and integrated with microfluidics on an imaging platform for real-time detection of breast cancer extracellular vesicles encompassing exosomes. The optofluidic system has high sensing performance with nearly 70 1/RIU figure-of-merit enabling detection of on average 0.41 nanoparticle/µm2 and real-time measurements of extracellular vesicles binding from down to 204 femtomolar solutions. Our biosensors provide the robustness of spectrometric approaches while substituting complex instrumentation with a single-wavelength light source and a complementary-metal-oxide-semiconductor camera, paving the way toward miniaturized devices for point-of-care diagnostics.

scholarly journals Microchip Transfer Process for Implantable Flexible Bioelectronic Devices

2021 ◽  
Vol 7 (2) ◽  
pp. 41-44
Author(s):  
Julien Martens ◽  
Calogero Gueli ◽  
Max Eickenscheidt ◽  
Thomas Stieglitz
Keyword(s):  
Transfer Process ◽  
Microelectromechanical Systems ◽  
Sacrificial Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Superficial Layer ◽  
Oxide Semiconductor ◽  
Accelerated Ageing ◽  
Post Processing ◽  
Silicon Chips

Abstract The demands on flexible implants for recording of neural signals and electrical stimulating have increased in recent years with regard to their functionality, miniaturization, and spatial resolution. These requirements can be met best by embedding powerful complementary metal oxide semiconductor (CMOS) microchips into thin biocompatible polymer substrates. So-called chip-in-foil systems thus combine mechanical properties of a polymer substrate and performance of CMOS technology. The development of a process for direct transfer of multiple CMOS microchips (edge length <400 μm) simultaneously into thin polyimide (PI) substrates is subject of this study. It allows the use of standard microelectromechanical systems (MEMS) processes for further levelled superficial layer build-up. This is achieved with the help of a silicon carrier wafer equipped with cavities for precise chip placement and a sacrificial layer to facilitate release of the chip-in-foil systems. In a post-processing step all silicon chips are thinned down to 100 μm. With this process a transfer yield of 100 % (n = 34) was achieved for the silicon chips on a die level. Chip rotational error on substrates was determined to be as low as 0.21° ± 0.10°. Die adhesion was examined by shear tests, resulting in shear strength of 58.1 MPa ± 13.7 MPa, which dropped to 15.2 MPa ± 10.5 MPa after accelerated ageing in 60 °C phosphate buffered saline solution (PBS) for 16 days (equivalent to 78 days at 37 °C). This study demonstrated a reliable microchip transfer process with low positioning error into flexible PI substrates with post-processing thinning of the dies. The use of a carrier silicon wafer allowed precise electrical interconnect fabrication with standard MEMS processing techniques and without handling of thin and fragile chips. These results are a prerequisite to meet needs of reliability and structural biocompatibility in implantable flexible bioelectronic devices.

scholarly journals An E-Band 21-dB Variable-Gain Amplifier with 0.5-V Supply in 40-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 804
Author(s):  
Gibeom Shin ◽  
Kyunghwan Kim ◽  
Kangseop Lee ◽  
Hyun-Hak Jeong ◽  
Ho-Jin Song
Keyword(s):  
Power Consumption ◽  
Frequency Band ◽  
Noise Figure ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Operating Frequency ◽  
Variable Gain Amplifier ◽  
Variable Gain ◽  
Operating Frequency Band ◽  
Shunt Capacitors

This paper presents a variable-gain amplifier (VGA) in the 68–78 GHz range. To reduce DC power consumption, the drain voltage was set to 0.5 V with competitive performance in the gain and the noise figure. High-Q shunt capacitors were employed at the gate terminal of the core transistors to move input matching points for easy matching with a compact transformer. The four stages amplifier fabricated in 40-nm bulk complementary metal oxide semiconductor (CMOS) showed a peak gain of 24.5 dB at 71.3 GHz and 3‑dB bandwidth of more than 10 GHz in 68–78 GHz range with approximately 4.8-mW power consumption per stage. Gate-bias control of the second stage in which feedback capacitances were neutralized with cross-coupled capacitors allowed us to vary the gain by around 21 dB in the operating frequency band. The noise figure was estimated to be better than 5.9 dB in the operating frequency band from the full electromagnetic (EM) simulation.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Complete Ring Artifacts Reduction Procedure for Lab-Based X-ray Nano CT Systems

Sensors ◽  
2021 ◽  
Vol 21 (1) ◽  
pp. 238
Author(s):  
Jakub Šalplachta ◽  
Tomáš Zikmund ◽  
Marek Zemek ◽  
Adam Břínek ◽  
Yoshihiro Takeda ◽  
...  
Keyword(s):  
High Efficiency ◽  
Image Inpainting ◽  
Simulated Data ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Detection Accuracy ◽  
Reduction Procedure ◽  
X Ray ◽  
Artifacts Reduction ◽  
Ct Data

In this article, we introduce a new ring artifacts reduction procedure that combines several ideas from existing methods into one complex and robust approach with a goal to overcome their individual weaknesses and limitations. The procedure differentiates two types of ring artifacts according to their cause and character in computed tomography (CT) data. Each type is then addressed separately in the sinogram domain. The novel iterative schemes based on relative total variations (RTV) were integrated to detect the artifacts. The correction process uses the image inpainting, and the intensity deviations smoothing method. The procedure was implemented in scope of lab-based X-ray nano CT with detection systems based on charge-coupled device (CCD) and scientific complementary metal–oxide–semiconductor (sCMOS) technologies. The procedure was then further tested and optimized on the simulated data and the real CT data of selected samples with different compositions. The performance of the procedure was quantitatively evaluated in terms of the artifacts’ detection accuracy, the comparison with existing methods, and the ability to preserve spatial resolution. The results show a high efficiency of ring removal and the preservation of the original sample’s structure.

Computational study of the staircase molecular conductivity of polyoxovanadates adsorbed on Au(111)

2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf
Keyword(s):  
Metal Oxide ◽  
Computational Study ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Molecular Conduction ◽  
Conduction Properties ◽  
Molecular Conductivity

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.

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