scholarly journals On-Substrate Joule Effect Heating by Printed Micro-Heater for the Preparation of ZnO Semiconductor Thin Film

Micromachines ◽  
2020 ◽  
Vol 11 (5) ◽  
pp. 490
Author(s):  
Van-Thai Tran ◽  
Yuefan Wei ◽  
Hejun Du

Fabrication of printed electronic devices along with other parts such as supporting structures is a major problem in modern additive fabrication. Solution-based inkjet printing of metal oxide semiconductor usually requires a heat treatment step to facilitate the formation of target material. The employment of external furnace introduces additional complexity in the fabrication scheme, which is supposed to be simplified by the additive manufacturing process. This work presents the fabrication and utilization of micro-heater on the same thermal resistive substrate with the printed precursor pattern to facilitate the formation of zinc oxide (ZnO) semiconductor. The ultraviolet (UV) photodetector fabricated by the proposed scheme was successfully demonstrated. The performance characterization of the printed devices shows that increasing input heating power can effectively improve the electrical properties owing to a better formation of ZnO. The proposed approach using the on-substrate heating element could be useful for the additive manufacturing of functional material by eliminating the necessity of external heating equipment, and it allows in-situ annealing for the printed semiconductor. Hence, the integration of the printed electronic device with printing processes of other materials could be made possible.

Author(s):  
Arash Alex Mazhari ◽  
Randall Ticknor ◽  
Sean Swei ◽  
Stanley Krzesniak ◽  
Mircea Teodorescu

AbstractThe sensitivity of additive manufacturing (AM) to the variability of feedstock quality, machine calibration, and accuracy drives the need for frequent characterization of fabricated objects for a robust material process. The constant testing is fiscally and logistically intensive, often requiring coupons that are manufactured and tested in independent facilities. As a step toward integrating testing and characterization into the AM process while reducing cost, we propose the automated testing and characterization of AM (ATCAM). ATCAM is configured for fused deposition modeling (FDM) and introduces the concept of dynamic coupons to generate large quantities of basic AM samples. An in situ actuator is printed on the build surface to deploy coupons through impact, which is sensed by a load cell system utilizing machine learning (ML) to correlate AM data. We test ATCAM’s ability to distinguish the quality of three PLA feedstock at differing price points by generating and comparing 3000 dynamic coupons in 10 repetitions of 100 coupon cycles per material. ATCAM correlated the quality of each feedstock and visualized fatigue of in situ actuators over each testing cycle. Three ML algorithms were then compared, with Gradient Boost regression demonstrating a 71% correlation of dynamic coupons to their parent feedstock and provided confidence for the quality of AM data ATCAM generates.


2017 ◽  
Vol 135 ◽  
pp. 385-396 ◽  
Author(s):  
Umberto Scipioni Bertoli ◽  
Gabe Guss ◽  
Sheldon Wu ◽  
Manyalibo J. Matthews ◽  
Julie M. Schoenung

2015 ◽  
Vol 15 (6) ◽  
pp. 4591-4595 ◽  
Author(s):  
Wei Chen ◽  
Shiqiao Qin ◽  
Xue-Ao Zhang ◽  
Jingyue Fang ◽  
Guang Wang ◽  
...  

2015 ◽  
Vol 821-823 ◽  
pp. 512-515
Author(s):  
Alberto Salinaro ◽  
Kassem Alassaad ◽  
Dethard Peters ◽  
Peter Friedrichs ◽  
Gabriel Ferro

We report on the electrical characterization of the Metal-Oxide-Semiconductor (MOS) interfacerealized on in-situ Ge-doped n-type 4H-SiC epilayers grown by Chemical Vapour Deposition(CVD). In order to study the relevance of this novel material for MOSFET technology, and in particularwhether the Ge presence deteriorates the SiC/SiO2 interface, we investigated the electrical propertiesof MOS capacitors realized on this novel substrate. Capacitance-Voltage measurements, performedto determine the quality of the SiC/SiO2 interface, show that the interface traps concentration is notincreased by the Ge content. The current through the oxide layer, monitored to study the bulk oxidequality and the tunneling mechanisms, indicates that Fowler-Nordheim conduction occurs and that thesubstrate-to-oxide barrier for electrons is comparable to the reported values for the SiC/SiO2 system.


2020 ◽  
Vol 37 (2) ◽  
pp. 79-85 ◽  
Author(s):  
Witold Nawrot ◽  
Karol Malecha

Purpose The purpose of this paper is to review possibilities of implementing ceramic additive manufacturing (AM) into electronic device production, which can enable great new possibilities. Design/methodology/approach A short introduction into additive techniques is included, as well as primary characterization of structuring capabilities, dielectric performance and applicability in the electronic manufacturing process. Findings Ceramic stereolithography (SLA) is suitable for microchannel manufacturing, even using a relatively inexpensive system. This method is suitable for implementation into the electronic manufacturing process; however, a search for better materials is desired, especially for improved dielectric parameters, lowered sintering temperature and decreased porosity. Practical implications Relatively inexpensive ceramic SLA, which is now available, could make ceramic electronics, currently restricted to specific applications, more available. Originality/value Ceramic AM is in the beginning phase of implementation in electronic technology, and only a few reports are currently available, the most significant of which is mentioned in this paper.


Author(s):  
R. E. Herfert

Studies of the nature of a surface, either metallic or nonmetallic, in the past, have been limited to the instrumentation available for these measurements. In the past, optical microscopy, replica transmission electron microscopy, electron or X-ray diffraction and optical or X-ray spectroscopy have provided the means of surface characterization. Actually, some of these techniques are not purely surface; the depth of penetration may be a few thousands of an inch. Within the last five years, instrumentation has been made available which now makes it practical for use to study the outer few 100A of layers and characterize it completely from a chemical, physical, and crystallographic standpoint. The scanning electron microscope (SEM) provides a means of viewing the surface of a material in situ to magnifications as high as 250,000X.


Author(s):  
J. I. Bennetch

In a recent study of the superplastic forming (SPF) behavior of certain Al-Li-X alloys, the relative misorientation between adjacent (sub)grains proved to be an important parameter. It is well established that the most accurate way to determine misorientation across boundaries is by Kikuchi line analysis. However, the SPF study required the characterization of a large number of (sub)grains in each sample to be statistically meaningful, a very time-consuming task even for comparatively rapid Kikuchi analytical techniques.In order to circumvent this problem, an alternate, even more rapid in-situ Kikuchi technique was devised, eliminating the need for the developing of negatives and any subsequent measurements on photographic plates. All that is required is a double tilt low backlash goniometer capable of tilting ± 45° in one axis and ± 30° in the other axis. The procedure is as follows. While viewing the microscope screen, one merely tilts the specimen until a standard recognizable reference Kikuchi pattern is centered, making sure, at the same time, that the focused electron beam remains on the (sub)grain in question.


Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


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