scholarly journals Infinite Selectivity of Wet SiO2 Etching in Respect to Al

Micromachines ◽  
2020 ◽  
Vol 11 (4) ◽  
pp. 365
Author(s):  
Imrich Gablech ◽  
Jan Brodský ◽  
Jan Pekárek ◽  
Pavel Neužil
Keyword(s):  
Elevated Temperature ◽  
Sheet Resistance ◽  
Etch Rate ◽  
Microelectromechanical Systems ◽  
Sacrificial Layer ◽  
Wet Etching ◽  
Water Bath ◽  
Fume Hood ◽  
Etching Solution ◽  
Unconventional Method

We propose and demonstrate an unconventional method suitable for releasing microelectromechanical systems devices containing an Al layer by wet etching using SiO2 as a sacrificial layer. We used 48% HF solution in combination with 20% oleum to keep the HF solution water-free and thus to prevent attack of the Al layer, achieving an outstanding etch rate of thermally grown SiO2 of ≈1 µm·min−1. We also verified that this etching solution only minimally affected the Al layer, as the chip immersion for ≈9 min increased the Al layer sheet resistance by only ≈7.6%. The proposed etching method was performed in an ordinary fume hood in a polytetrafluorethylene beaker at elevated temperature of ≈70 °C using water bath on a hotplate. It allowed removal of the SiO2 sacrificial layer in the presence of Al without the necessity of handling highly toxic HF gas.

scholarly journals Etching of Crystalline Silicon in Thermal Environment

2011 ◽  
Vol 2 ◽  
pp. 38-42
Author(s):  
Shobha Kanta Lamichhane ◽  
Min Raj Lamsal
Keyword(s):  
Process Control ◽  
Etch Rate ◽  
Crystalline Silicon ◽  
Thermal Environment ◽  
Anisotropic Etching ◽  
Wet Etching ◽  
Control Technique ◽  
Etching Solution ◽  
Wet Etch ◽  
Process Control Technique

Thin wafer have become a basic need for a wide variety of new microelectronic products. Wafers that have been thinned using wet etch process on the backside have less stress compared with standard mechanical back grinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control technique for maintaining a consistent etch rate as a function of time and wafer processed.Keywords: Isotropic and anisotropic etching; MEMS; SOI; LPCVDThe Himalayan Physics Vol.2, No.2, May, 2011Page: 38-42Uploaded Date: 1 August, 2011

Process Control for Wet Etching for Silicon Wafer Thinning

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001030-001053
Author(s):  
Laura Mauer ◽  
Herman Itzkowitz ◽  
John Taddei
Keyword(s):  
Process Control ◽  
Silicon Wafer ◽  
Etch Rate ◽  
Wet Etching ◽  
Etching Solution ◽  
Control Techniques ◽  
Cost Of Ownership ◽  
The Cost ◽  
Wet Etch ◽  
Wafer Thinning

Thin wafers have become a basic need for a wide variety of new microelectronic products. Thinner die are being required to fit into thinner packages. Wafers that have been thinned using a final wet etch process on the backside have less stress compared with standard mechanical backgrinding. Isotropic wet etching of silicon is typically done with a mixture of nitric and hydrofluoric acids along with the addition of chemicals to adjust for viscosity and surface wettability for single wafer spin processing. As the silicon is etched and incorporated in the etching solution the etch rate will decrease with time. This variation has been modeled. The focus of this paper is to compare the process control techniques for maintaining a consistent etch rate as a function of time and wafers processed. The models allow for either the time to be extended, chemicals to be replenished or a combination of these. Results will be presented including the cost of ownership for each scenario.

Fabrication and Test of 3C-SiC Electrostatic Resonators

2007 ◽  
Vol 556-557 ◽  
pp. 949-952
Author(s):  
Marcel Placidi ◽  
Phillippe Godignon ◽  
Jaume Esteve ◽  
Narcis Mestres ◽  
Gabriel Abadal
Keyword(s):  
Sacrificial Layer ◽  
Ambient Condition ◽  
Wet Etching ◽  
Test Results ◽  
Si Substrate ◽  
Capacitive Current ◽  
Step Process ◽  
Electrostatically Actuated ◽  
Icp Etching ◽  
Resonance Frequencies

Silicon Carbide has proven its relevance for various MEMS and sensors devices applications. This paper presents the fabrication and the first test results of 3C-SiC electrostatic resonators actuated by applying a combination of AC and DC voltages. The recipe used for the fabrication has taken the advantage of the starting material, 3C-SiC grown on Si, which allows us to use the Si substrate as sacrificial layer to release the structures. Resonators have been fabricated by a two-step process, combining RIE ICP etching with HF wet etching. Resonators have been successfully electrostatically actuated in air-ambient condition. The resonance frequencies were clearly identified, although capacitive current created by actuation was not detected.

Feature Size and Density Effects in Wet Selective Etching of GaAs/AlAs p-HEMT Structures with Organic Acid - Peroxide Solutions.

2003 ◽  
Vol 799 ◽  
Author(s):  
Vinay S. Kulkarni ◽  
Kanti Prasad ◽  
William Quinn ◽  
Frank Spooner ◽  
Changmo Sung
Keyword(s):  
Surface Morphology ◽  
Organic Acid ◽  
Etch Rate ◽  
Low Noise ◽  
Wet Etching ◽  
Low Noise Amplifiers ◽  
Etch Depth ◽  
Feature Size ◽  
Selective Etch ◽  
Etch Stop

ABSTRACTPseudomorphic HEMT (p-HEMT) devices are used in a number of wireless communication applications including power amplifiers in the 17–50 GHz range, low noise amplifiers and switches. Selective wet etching is often used to form the gate regions of these devices to avoid plasma damage associated with dry etching. We have investigated the wet etching of small (8μm to 0.5μm) features with organic acid - hydrogen peroxide solutions. Two acid solutions were used as a selective etchant for GaAs using AlAs etch stop layers in a p-HEMT structure grown by MBE. The etched features were characterized by AFM, SEM, and TEM techniques. The etch depth uniformity and reproducibility were found to depend on a number of factors including feature size, feature density, etching chemistry, agitation and surface tension. When features with a range of size and density were placed in close proximity in a layout we found that the etch rate of the different features was a function of density, size and most importantly the etch chemistry. One etchant solution exhibited a 12% difference in etch rate from the smallest feature to the largest, while another solution exhibited uniform etching of all features regardless of size or density. Both solutions produced specular etched surfaces in GaAs and AlGaAs. However, the AlAs etch stop showed a non-uniform surface morphology after etching. The surface morphology of the AlAs etch stop is one factor that limits the over etch which can be designed into the process. The most important factors to be considered in designing a selective etch process will be presented.

Study on sapphire microstructure processing technology based on wet etching

2017 ◽  
Vol 31 (07) ◽  
pp. 1741004 ◽  
Author(s):  
Ying-Qi Shang ◽  
Hong Qi ◽  
Yun-Long Ma ◽  
Ya-Lin Wu ◽  
Yan Zhang ◽  
...  
Keyword(s):  
Surface Roughness ◽  
Process Parameters ◽  
Etching Rate ◽  
Wet Etching ◽  
Processing Technology ◽  
Light Extraction Efficiency ◽  
Etching Time ◽  
Etching Solution ◽  
Sapphire Surface ◽  
Optical Pressure

Aiming at the problem that sapphire surface roughness is quite large after wet etching in sapphire microstructure processing technology, we optimize the wet etching process parameters, study on the influences of concentration and temperature of etching solution and etching time on the sapphire surface roughness and etching rate, choose different process parameters for the experiment and test and analyze the sapphire results after wet etching. Aiming at test results, we also optimize the process parameters and do experiment. Experimental results show that, after optimizing the parameters of etching solution, surface roughness of etched sapphire is 0.39 nm, effectively with reduced surface roughness, improved light extraction efficiency and meeting the production requirements of high-precision optical pressure sensor.

Effects of etching holes on complementary metal oxide semiconductor–microelectromechanical systems capacitive structure

2012 ◽  
Vol 24 (3) ◽  
pp. 310-317 ◽  
Author(s):  
Wei-Hsiang Tu ◽  
Wen-Chang Chu ◽  
Chih-Kung Lee ◽  
Pei-Zen Chang ◽  
Yuh-Chung Hu
Keyword(s):  
Metal Oxide ◽  
Microelectromechanical Systems ◽  
Sacrificial Layer ◽  
Estimation Method ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Fringe Field ◽  
Large Area ◽  
Fringing Field

Etching the large area of sacrificial layer under the microstructure to be released is a common method used in microelectromechanical systems technology. In order to completely release the microstructures, many etching holes are often required on the microstructure to enable the etchant to completely etch the sacrificial layer. However, the etching holes often alter the electromechanical properties of the micro devices, especially capacitive devices, because the fringe fields induced by the etching holes can significantly alter the electrical properties. This article is aimed at evaluating the fringe field capacitance caused by etching holes on microstructures. The authors aim to find a general capacitance compensation formula for the fringe capacitance of etching holes by the use of ANSYS simulation. According to the simulation results, the design of a capacitive structure with small etching holes is recommended to prevent an extreme capacitance decrease. In conclusion, this article provides a fringing field capacitance estimation method that shows the capacitance compensation tendency of the design of etching holes; this method is expected to be applicable to the design in capacitive devices of complementary metal oxide semiconductor–microelectromechanical systems technology.

Study on the Etching Technique of Non-Photosensitive Polyimide

2015 ◽  
Vol 645-646 ◽  
pp. 163-168
Author(s):  
Rui Lei ◽  
Wei Guo Liu ◽  
Chang Long Cai ◽  
Shun Zhou ◽  
Jing Nie ◽  
...  
Keyword(s):  
Bias Voltage ◽  
Sacrificial Layer ◽  
Dry Etching ◽  
Wet Etching ◽  
Etching Process ◽  
Good Effect ◽  
Floating Structure ◽  
Etching Technique ◽  
Layer Material ◽  
Etching Effect

Polyimide is often used as a sacrificial layer material to make floating structure. Polyimide is also divided into photosensitive and non-photosensitive type; photosensitive polyimide currently has more negative photoresist and poor performance in many ways. Compared with photosensitive polyimide, the non-photosensitive type has low stress, stable performance and other advantages, so non-photosensitive polyimide has been chosen as a sacrificial layer material. To achieve the graphical function and release sacrificial layer, A deeply research was made in this dissertation makes on wet etching and dry etching. By controlling the wet etching process of prebake condition, exposure and developing time, and oxygen dry etching process of etching power, bias voltage and other key process parameters, a good sacrificial layer graph and etching effect have been got. Finally, it can be concluded that when the prebake conditions for 105°C, 8min and times of exposure and developing were 11s and 29s, the non-photosensitive polyimide wet etching effect is the best; when the etching power is 1000w, an oxygen flux rate is 50sccm, the reaction pressure is 30mTorr, the bias voltage is 140v, oxygen dry etching has a good effect.

Investigation on Wet Etching 4H-SiC Damaged by Ion Implantation

2017 ◽  
Vol 897 ◽  
pp. 367-370
Author(s):  
Sophie Guillemin ◽  
Romain Esteve ◽  
Christian Heidorn ◽  
Gerald Unegg ◽  
Gerald Reinwald ◽  
...  
Keyword(s):  
Monte Carlo ◽  
Ion Implantation ◽  
Monte Carlo Simulations ◽  
Wet Etching ◽  
Etching Solution ◽  
Experimental Findings ◽  
Wet Etch ◽  
Ion Implanted

In this work investigation on wet etching of ion implanted 4H-SiC has been performed. Starting with the search for a suitable etching solution is followed by investigations on how to damage 4H-SiC in an efficient way involving different implantation species in various doses. With the help of Monte Carlo simulations a model for the experimental findings is proposed to derive the limitations for the wet etch capability.

An Etch-Back Planarization Process Using A Sacrificial Polymide Layer

1991 ◽  
Vol 240 ◽  
Author(s):  
J. R. Lothian ◽  
T. R. Fullowan
Keyword(s):  
Surface Topography ◽  
Dielectric Layer ◽  
Rate Ratio ◽  
Parallel Plate ◽  
Etch Rate ◽  
Dielectric Film ◽  
Sacrificial Layer ◽  
Loading Effect ◽  
Planarization Process ◽  
Etching System

ABSTRACTAn etch-back polymide planarization process for the emitter contact of AlGaAs/GaAs HBTs using PC-1500 is presented. The degree of surface topography has a major impact on the yield in HBT fabrication. A planarization process using a spin-on sacrificial layer to produce a planar interlevel dielectric layer would be very beneficial in allowing thicker and more uniform emitter contacts therefore enhancing the yield and current handling capability. The PC-1500 polymer flows at 200°C and provides a much better planarity than regular photoresist. For patterns from -3 μm to 250 this polymer can achieve 80% to 92% planarity. The wafers were etched in a parallel plate, single wafer reactive ion-etching system with a mixture of oxygen and Freon-14. The etch rate of this polymer increased with the oxygen content of the discharge then became fairly constant at high O2 concentrations while the etch rate of the underlying dielectric film (SiN) was proportional to the Freon 14 content. This new polymer shows little loading effect. A 1:1 etch rate ratio of SiN to PC-1500 was established for good planarity.

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