scholarly journals An Interface ASIC for MEMS Vibratory Gyroscopes with Nonlinear Driving Control

Micromachines ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 270 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Liang Yin ◽  
Yuan Gao ◽  
Wei Bai ◽  
...  

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm2. Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

Sensors ◽  
2020 ◽  
Vol 20 (19) ◽  
pp. 5460 ◽  
Author(s):  
Risheng Lv ◽  
Qiang Fu ◽  
Weiping Chen ◽  
Liang Yin ◽  
Xiaowei Liu ◽  
...  

This paper proposes a solution for sensing spatial angular velocity. A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented. The technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom (DOF). Self-excited digital closed loop drives the proof mass in sensing elements at its inherent resonant frequency for Coriolis force generation during angular rotation. The analog front ends in both drive and sense loops are comprised of low-noise charge-voltage (C/V) converters and multi-channel incremental zoom analog-to-digital converters (ADC), so that capacitance variation between combs induced by mechanical motion is transformed into digital voltage signals. Other circuitry elements, such as loop controlling and accurate demodulation modules, are all implemented in digital logics. Automatic amplitude stabilization is mainly realized by peak detection and proportion-integration (PI) control. Nonlinear digital gain adjustment is designed for rapid establishment of resonance oscillation and linearity improvement. Manufactured in a standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) technology, this design achieves a bias instability of 2.1°/h and a nonlinearity of 0.012% over full-scale range.


Micromachines ◽  
2020 ◽  
Vol 11 (1) ◽  
pp. 65
Author(s):  
Wenhao Zhi ◽  
Qingxiao Quan ◽  
Pingping Yu ◽  
Yanfeng Jiang

Photodiode is one of the key components in optoelectronic technology, which is used to convert optical signal into electrical ones in modern communication systems. In this paper, an avalanche photodiode (APD) is designed and fulfilled, which is compatible with Taiwan Semiconductor Manufacturing Company (TSMC) 45-nm standard complementary metal–oxide–semiconductor (CMOS) technology without any process modification. The APD based on 45 nm process is beneficial to realize a smaller and more complex monolithically integrated optoelectronic chip. The fabricated CMOS APD operates at 850 nm wavelength optical communication. Its bandwidth can be as high as 8.4 GHz with 0.56 A/W responsivity at reverse bias of 20.8 V. Its active area is designed to be 20 × 20 μm2. The Simulation Program with Integrated Circuit Emphasis (SPICE) model of the APD is also proposed and verified. The key parameters are extracted based on its electrical, optical and frequency responses by parameter fitting. The device has wide potential application for optical communication systems.


2021 ◽  
Vol 2108 (1) ◽  
pp. 012034
Author(s):  
Haoran Xu ◽  
Jianghua Ding ◽  
Jian Dang

Abstract Known as complementary symmetrical metal oxide semiconductor (cos-mos), complementary metal oxide semiconductor is a metal oxide semiconductor field effect transistor (MOSFET) manufacturing process, which uses complementary and symmetrical pairs of p-type and n-type MOSFETs to realize logic functions. CMOS technology is used to build integrated circuit (IC) chips, including microprocessors, microcontrollers, memory chips (including CMOS BIOS) and other digital logic circuits. CMOS technology is also used in analog circuits, such as image sensors (CMOS sensors), data converters, RF circuits (RF CMOS), and highly integrated transceivers for various types of communications. Based on multisim 14.0 and cadence, the characteristics and performance of CMOS inverter are studied by simulation.


1989 ◽  
Vol 67 (4) ◽  
pp. 184-189 ◽  
Author(s):  
M. Parameswaran ◽  
Lj. Ristic ◽  
A. C. Dhaded ◽  
H. P. Baltes ◽  
W. Allegretto ◽  
...  

Complementary metal oxide semiconductor (CMOS) technology is one of the leading fabrication technologies of the semiconductor integrated-circuit industry. We have discovered features inherent in the standard CMOS fabrication process that lend themselves to the manufacturing of micromechanical structures for sensor applications. In this paper we present an unconventional layout design methodology that allows us to exploit the standard CMOS process for producing microbridges. Two types of microbridges, bare polysilicon microbridges and sandwiched oxide microbridges, have been manufactured by first implementing a special layout design in an industrial digital CMOS process, followed by a postprocessing etching step.


2020 ◽  
Vol 20 (3) ◽  
pp. 207-212
Author(s):  
Yonggoo Lee ◽  
Bomson Lee

A tunable bondwire inductor (TBI) with high-quality factor and wide tuning range is presented. The proposed TBI is fabricated on a single chip by combining a single-pole four-throw (SP4T) switch integrated circuit (IC) and four bondwire inductors on a package substrate. The SP4T switch IC is fabricated using 180 nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The fabricated TBI chip exhibits a 521% tuning range of inductance from 1.77 to 11 nH at 0.1 GHz and a relatively high-quality factor. To the knowledge of the authors, the results of this work demonstrate the best combined performance of inductance tuning range and quality factor.


2021 ◽  
Vol 50 (16) ◽  
pp. 5540-5551
Author(s):  
Almudena Notario-Estévez ◽  
Xavier López ◽  
Coen de Graaf

This computational study presents the molecular conduction properties of polyoxovanadates V6O19 (Lindqvist-type) and V18O42, as possible successors of the materials currently in use in complementary metal–oxide semiconductor (CMOS) technology.


Micromachines ◽  
2021 ◽  
Vol 12 (5) ◽  
pp. 551
Author(s):  
Zhongjian Bian ◽  
Xiaofeng Hong ◽  
Yanan Guo ◽  
Lirida Naviner ◽  
Wei Ge ◽  
...  

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.


1998 ◽  
Vol 37 (Part 1, No. 3B) ◽  
pp. 1050-1053 ◽  
Author(s):  
Masayasu Miyake ◽  
Toshio Kobayashi ◽  
Yutaka Sakakibara ◽  
Kimiyoshi Deguchi ◽  
Mitsutoshi Takahashi

2016 ◽  
Vol 8 (3) ◽  
pp. 399-404 ◽  
Author(s):  
Boris Moret ◽  
Nathalie Deltimple ◽  
Eric Kerhervé ◽  
Baudouin Martineau ◽  
Didier Belot

This paper presents a 60 GHz reconfigurable active phase shifter based on a vector modulator implemented in 65 nm complementary metal–oxide–semiconductor technology. This circuit is based on the recombination of two differential paths in quadrature. The proposed vector modulator allows us to generate a phase shift between 0° and 360°. The voltage gain varies between −13 and −9 dB in function of the phase shift generated with a static consumption between 26 and 63 mW depending on its configuration.


Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.


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