scholarly journals Full-Differential Folded-Cascode Front-End Receiver Amplifier Integrated Circuit for Capacitive Micromachined Ultrasonic Transducers

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 88
Author(s):  
Yiheng Du ◽  
Changde He ◽  
Guowei Hao ◽  
Wendong Zhang ◽  
Chenyang Xue
Keyword(s):  
Power Consumption ◽  
Ultrasonic Transducer ◽  
Equivalent Circuit Model ◽  
Center Frequency ◽  
Gain Bandwidth ◽  
Correct Operation ◽  
Op Amp ◽  
Front End ◽  
Trade Offs ◽  
Folded Cascode

This paper describes the design of a front-end receiver amplifier for capacitive micromachined ultrasonic transducer (CMUT). The proposed operational amplifier (op amp) consists of a full differential folded-cascode amplifier stage followed by a class AB output stage. A feedback resistor is applied between the input and the output of the op amp to make a transimpedance amplifier. We analyzed the equivalent circuit model of the CMUT element operating in the receiving mode and obtained the static output impedance and center frequency characteristics of the CMUT. The op amp gain, bandwidth, noise, and power consumption trade-offs are discussed in detail. The amplifier was fabricated using GlobalFoundries 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. The open loop gain of the amplifier is approximately 65 dB, and its gain bandwidth product is approximately 29.5 MHz. The measured input reference noise current was 56 nA/√Hz@3 MHz. The amplifier chip area is 325 μm × 150 μm and the op amp is powered by 3.3 V, the static power consumption is 11 mW. We verified the correct operation of our amplifier with CMUT and echo-pulse shown that the CMUT center frequency is 3 MHz with 92% fractional bandwidth.

Study and Design of an Ultrasonic Flow Tomographic Front-End Multi Level Measurement System

2014 ◽  
Vol 69 (8) ◽  
Author(s):  
Goh Chiew Loon ◽  
Ruzairi Abdul Rahim ◽  
Suzanna Ridzuan Aw ◽  
Fazlul Rahman Mohd Yunus ◽  
Nor Muzakkir Nor Ayob ◽  
...  
Keyword(s):  
Ultrasonic Transducer ◽  
Rapid Evolution ◽  
Flow Visualisation ◽  
Ultrasonic Tomography ◽  
Basic Operation ◽  
Measurement Capability ◽  
Front End ◽  
Trade Offs ◽  
Multi Level ◽  
Primary Focus

With the rapid evolution of electro-acoustical technology, ultrasonic tomography has made considerable progress in industry. An ultrasonic tomography system provides non-invasive and non-intrusive flow visualisation that enhances the understanding of fluid flow processes. The function of ultrasonic tomography is to continuously monitor the dynamics of liquid flow without interrupting the flow. The ultrasonic tomography technique is fully supported by a front-end hardware system. The front end is defined as all the hardware circuitries, including the ultrasonic transducer up to the Analogue-to-Digital Convertors (ADCs), even though the primary focus is the analogue signal processing components. We present here the challenges and trade-offs in the implementation of a front-end system by first explaining the basic operation of such a system, and then indicating what particular performance parameters are needed to ensure optimal system operation. Based on the results from our research studies, we propose an improved front-end multi-level solution that is more accurate than previous solutions and provides real-time measurement capability.

Power Efficient Implementation of Low Noise CMOS LC VCO using 32nm Technology for RF Applications

2018 ◽  
Vol 6 (8) ◽  
pp. 53
Author(s):  
Shitesh Tiwari ◽  
Sumant Katiyal ◽  
Parag Parandkar
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Low Voltage ◽  
Performance Comparison ◽  
Low Noise ◽  
Center Frequency ◽  
Voltage Controlled Oscillator ◽  
Low Phase Noise ◽  
Lc Vco

Voltage Controlled Oscillator (VCO) is an integral component of most of the receivers such as GSM, GPS etc. As name indicates, oscillation is controlled by varying the voltage at the capacitor of LC tank. By varying the voltage, VCO can generate variable frequency of oscillation. Different VCO Parameters are contrasted on the basis of phase noise, tuning range, power consumption and FOM. Out of these phase noise is dependent on quality factor, power consumption, oscillation frequency and current. So, design of LC VCO at low power, low phase noise can be obtained with low bias current at low voltage.  Nanosize transistors are also contributes towards low phase noise. This paper demonstrates the design of low phase noise LC VCO with 4.89 GHz tuning range from 7.33-11.22 GHz with center frequency at 7 GHz. The design uses 32nm technology with tuning voltage of 0-1.2 V. A very effective Phase noise of -114 dBc / Hz is obtained with FOM of -181 dBc/Hz. The proposed work has been compared with five peer LC VCO designs working at higher feature sizes and outcome of this performance comparison dictates that the proposed work working at better 32 nm technology outperformed amongst others in terms of achieving low Tuning voltage and moderate FoM, overshadowed by a little expense of power dissipation. 

Design and Experiment of Capacitive Micromachined Ultrasonic Transducer Array for High-Frequency Underwater Imaging

2020 ◽  
Vol 13 ◽  
Author(s):  
Yuanyu Yu ◽  
Jiujiang Wang ◽  
Xin Liu ◽  
Sio Hang Pun ◽  
Weibao Qiu ◽  
...  
Keyword(s):  
Ultrasound Imaging ◽  
High Frequency ◽  
Ultrasonic Transducer ◽  
Center Frequency ◽  
Design Parameters ◽  
Underwater Imaging ◽  
Release Process ◽  
Steel Wires ◽  
Capacitive Micromachined Ultrasonic Transducer ◽  
Frequency Ultrasound

Background:: Ultrasound is widely used in the applications of underwater imaging. Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate to the traditional piezoelectric ultrasonic transducer. In underwater ultrasound imaging, better resolutions can be achieved with a higher frequency ultrasound. Therefore, a CMUT array for high-frequency ultrasound imaging is proposed in this work. Methods:: Analytical methods are used to calculate the center frequency in water and the pull-in voltage for determining the operating point of CMUT. Finite element method model was developed to finalize the design parameters. The CMUT array was fabricated with a five-mask sacrificial release process. Results:: The CMUT array owned an immersed center frequency of 2.6 MHz with a 6 dB fractional bandwidth of 123 %. The pull-in voltage of the CMUT array was 85 V. An underwater imaging experiment was carried out with the target of three steel wires. Conclusion:: In this study, we have developed CMUT for high-frequency underwater imaging. The experiment showed that the CMUT can detect the steel wires with the diameter of 100 μm and the axial resolution was 0.582 mm, which is close to one wavelength of ultrasound in 2.6 MHz.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

2020 ◽  
Vol 37 (4) ◽  
pp. 205-213
Author(s):  
Norhamizah Idros ◽  
Zulfiqar Ali Abdul Aziz ◽  
Jagadheswaran Rajendran
Keyword(s):  
Operational Amplifier ◽  
Open Loop ◽  
Cmos Process ◽  
Silicon Area ◽  
Content Type ◽  
Op Amp ◽  
Dc Gain ◽  
Input Range ◽  
Folded Cascode ◽  
The Impact

Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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