scholarly journals Study of a Gate-Engineered Vertical TFET with GaSb/GaAs0.5Sb0.5 Heterojunction

Materials ◽  
2021 ◽  
Vol 14 (6) ◽  
pp. 1426
Author(s):  
Haiwu Xie ◽  
Yanning Chen ◽  
Hongxia Liu ◽  
Dan Guo
Keyword(s):  
Field Effect Transistor ◽  
Performance Enhancement ◽  
Source Region ◽  
Gain Bandwidth ◽  
Source Voltage ◽  
Effect Transistor ◽  
Work Functions ◽  
Tunnel Field Effect Transistor ◽  
And Control ◽  
Dual Material

It is well known that the vertical tunnel field effect transistor (TFET) is easier to fabricate than the conventional lateral TFETs in technology. Meanwhile, a lightly doped pocket under the source region can improve the subthreshold performance of the vertical TFETs. This paper demonstrates a dual material gate heterogeneous dielectric vertical TFET (DMG-HD-VTFET) with a lightly doped source-pocket. The proposed structure adopts a GaSb/GaAs0.5Sb0.5 heterojunction at the source and pocket to improve the band-to-band tunneling (BTBT) rate; at the same time, the gate electrode is divided into two parts, namely a tunnel gate (M1) and control gate (M2) with work functions ΦM1 and ΦM2, where ΦM1 > ΦM2. In addition, further performance enhancement in the proposed device is realized by a heterogeneous dielectric corresponding to a dual material gate. Simulation results indicate that DMG-HD-VTFET and HD-VTFET possess superior metrics in terms of DC (Direct Current) and RF (Radio Frequency) performance as compared with conventional VTFET. As a result, the ON-state current of 2.92 × 10−4 A/μm, transconductance of 6.46 × 10−4 S/μm, and average subthreshold swing (SSave) of 18.1 mV/Dec at low drain voltage can be obtained. At the same time, DMG-HD-VTFET could achieve a maximum fT of 459 GHz at 0.72 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 35 GHz at Vgs = 0.6 V, respectively. So, the proposed structure will have a great potential to boost the device performance of traditional vertical TFETs.

scholarly journals Design and Performance Enhancement of Gate-on-Source PNPN Doping–Less Vertical Nanowire TFET

2021 ◽  
Author(s):  
Kritika Lal ◽  
Anushka Verma ◽  
Pradeep Kumar ◽  
Naveen Kumar ◽  
S. Intekhab Amin ◽  
...  
Keyword(s):  
Performance Enhancement ◽  
Specific Work ◽  
Heavily Doped ◽  
Effect Transistor ◽  
Work Functions ◽  
Tunnel Field Effect Transistor ◽  
And Performance ◽  
Output Characteristics ◽  
Output Conductance ◽  
Intrinsic Gain

Abstract This paper outlines the study of a Doping-Less Vertical Nanowire Tunnel Field Effect Transistor (DLVNWTFET) with a p-i-n structure, aiming to enhance the performance of this device. The proposed device, which is a p-n-p-n configured DLVNWTFET, switches with a steeper sub-threshold slope while keeping the Off-state current (IOFF) and threshold-voltage (VTH) low and also improves the On-state current (ION) of the device; which is one of the crucial problems in TFETs. The nanowire TFET structure is vertically grown on an intrinsic silicon wafer. This vertical structure eases the fabrication process and also helps in the implementation of Charge-Plasma (CP) Technique. It is a process by which electrodes of specific work functions are used to induce charges in the Source (P) and Drain (N) regions. To realize the p-n-p-n configured structure, pocketing technique is used where the N+ heavily doped pocket is introduced between the Source and the Channel through CP concept. Upon calculation and comparison of various analog and device parameters, the proposed p-n-p-n structure shows better performance in contrast to the p-i-n DLVNWTFET. Analysis of the performance of the two configurations has been done, comparing various parameters like transconductance (Gm), output conductance (GD), transfer characteristics (ID–VGS), output characteristics (ID–VDS), cut-off frequency (fT), total gate capacitance (CGG) and intrinsic gain.

Structural Modification of Doped Tunnel Field Effect Transistor for Enhanced Conduction Current and Lower Subthreshold Swing

2019 ◽  
Vol 14 (11) ◽  
pp. 1539-1547
Author(s):  
Deepak Soni ◽  
Amit Kumar Behera ◽  
Dheeraj Sharma ◽  
Dip Prakash Samajdar ◽  
Dharmendra Singh Yadav
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Layer ◽  
Source Region ◽  
Subthreshold Swing ◽  
Electrical Characteristics ◽  
Gate Electrode ◽  
Effect Transistor ◽  
Tunnel Field Effect Transistor ◽  
Rf Performance

The material solubility in the source region and abrupt source/channel junction profile are the major concern which is responsible for the improvement of the electrical characteristics of conventional physical doped tunnel field effect transistor (PD-TFET). For this, an additional negatively polarised electrode is mounted in P+ (source) – N (channel) – N+ (drain) structure over the source region to overcome material solubility. This improves the electrical characteristics of the device. Along with this, we have implanted a low workfunction metal layer (ML) in the oxide layer under the gate electrode for creating more abruptness at the junction to improve the subthreshold swing (SS) of the device. Thus, the proposed concept improves the DC/RF performance of the doped TFET device. Further to this, the optimization of metal layer workfunction and misalignment of metal layer in TFET have been performed to get optimum device characteristics. In addition to this, for the suppression of ambipolar behaviour, gate electrode is shorted from the drain side. Due to short length of gate electrode tunneling barrier width at the drain/channel junction increases, hence the tunneling probability decreases which reduces the ambipolar current to parasitic current. Shortening of gate electrode also improves the RF performance.

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