scholarly journals RDAMS: An Efficient Run-Time Approach for Memory Fault and Hardware Trojans Detection

Information ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 169
Author(s):  
Jian Wang ◽  
Ying Li
Keyword(s):  
Human Life ◽  
Performance Degradation ◽  
Hardware Trojans ◽  
Detection Approach ◽  
Detection Mode ◽  
Latency Response ◽  
Run Time ◽  
Block Based ◽  
Iot Devices ◽  
On Chip

Ensuring the security of IoT devices and chips at runtime has become an urgent task as they have been widely used in human life. Embedded memories are vital components of SoC (System on Chip) in these devices. If they are attacked or incur faults at runtime, it will bring huge losses. In this paper, we propose a run-time detection architecture for memory security (RDAMS) to detect memory threats (fault and Hardware Trojans attack). The architecture consists of a Security Detection Core (SDC) that controls and enforces the detection procedure as a “security brain”, and a memory wrapper (MEM_wrapper) which interacts with memory to assist the detection. We also design a low latency response mechanism to solve the SoC performance degradation caused by run-time detection. A block-based multi-granularity detection approach is proposed to render the design flexible and reduce the cost in implementation using the FPGA’s dynamic partial reconfigurable (DPR) technology, which enables online detection mode reconfiguration according to the requirements. Experimental results show that RDAMS can correctly detect and identify 10 modeled memory faults and two types of Hardware Trojans (HTs) attacks without leading a great performance degradation to the system.

Run Time Mitigation of Performance Degradation Hardware Trojan Attacks in Network on Chip

2018 ◽  
Author(s):  
Manoj Kumar J.Y.V. ◽  
Ayas Kanta Swain ◽  
Sudeendra Kumar ◽  
Sauvagya Ranjan Sahoo ◽  
Kamalakanta Mahapatra
Keyword(s):  
Performance Degradation ◽  
Network On Chip ◽  
Hardware Trojan ◽  
Run Time ◽  
On Chip

Design of Interplanetary Observation Terminal based on All Programmable System-on-Chip

2021 ◽  
Author(s):  
Haonan Jin ◽  
Lesheng He ◽  
Liang Dong ◽  
Yongliang Tan ◽  
Qingyang Kong
Keyword(s):  
Solar Wind ◽  
Human Life ◽  
Average Power ◽  
Experimental Tests ◽  
System On Chip ◽  
High Time Resolution ◽  
Processing Scheme ◽  
Gigabit Ethernet ◽  
System Memory ◽  
On Chip

The drastic changes in the solar wind will cause serious harm to human life. Monitoring interplanetary scintillation (IPS) can predict solar wind activity, thereby effectively reducing the harm caused by space weather. Aiming at the problem of the lack of the ability to observe IPS phenomenon of the 40-meter radio telescope at the Yunnan Astronomical Observatory of China in the frequency band around 300MHz, an IPS real-time acquisition and processing scheme based on all programmable system-on-chip(APSoC) was proposed. The system calculates the average power of 10ms IPS signal in PL-side and transmits it to the system memory through AXI4 bus. PS-side reads the data, takes logarithms, packages it, and finally transmits it to the LabVIEW host computer through gigabit Ethernet UDP mode for display and storage. Experimental tests show that the system functions correctly, and the PL-side power consumption is only 1.955 W, with a high time resolution of 10ms, and no data is lost in 24 hours of continuous observation, with good stability. The system has certain application value in IPS observation.

scholarly journals Direct Ink Writing of Materials for Electronics-Related Applications: A Mini Review

2021 ◽  
Vol 8 ◽  
Author(s):  
Zhenzhong Hou ◽  
Hai Lu ◽  
Ying Li ◽  
Laixia Yang ◽  
Yang Gao
Keyword(s):  
Human Life ◽  
Electronic Devices ◽  
Electronic Components ◽  
Direct Ink Writing ◽  
Recent Developments ◽  
Print Materials ◽  
On Chip ◽  
Functional Components ◽  
Printing Techniques

Recently, the fabrication of electronics-related components via direct ink writing (DIW) has attracted much attention. Compared to the conventionally fabricated electronic components, DIW-printed ones have more complicated structures, higher accuracy, improved efficiency, and even enhanced performances that arise from well-designed architectures. The DIW technology allows directly print materials on a variety of flat substrates, even a conformal one, well suiting them to applications such as wearable devices and on-chip integrations. Here, recent developments in DIW printing of emerging components for electronics-related applications are briefly reviewed, including electrodes, electronic circuits, and functional components. The printing techniques, processes, ink materials, advantages, and properties of DIW-printed architectures are discussed. Finally, the challenges and outlooks on the manufacture of 3D structured electronic devices by DIW are outlined, pointing out future designs and developments of DIW technology for electronics-related applications. The combination of DIW and electronic devices will help to improve the quality of human life and promote the development of science and society.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

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