scholarly journals A High Throughput Hardware Architecture for Parallel Recursive Systematic Convolutional Encoders

Information ◽  
2019 ◽  
Vol 10 (4) ◽  
pp. 151
Author(s):  
Gabriele Meoni ◽  
Gianluca Giuffrida ◽  
Luca Fanucci
Keyword(s):  
High Throughput ◽  
Network Topology ◽  
Bit Error Rate ◽  
Error Rate ◽  
Field Programmable Gate Array ◽  
Input Data ◽  
Telecommunication Systems ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Convolutional Encoders

During the last years, recursive systematic convolutional (RSC) encoders have found application in modern telecommunication systems to reduce the bit error rate (BER). In view of the necessity of increasing the throughput of such applications, several approaches using hardware implementations of RSC encoders were explored. In this paper, we propose a hardware intellectual property (IP) for high throughput RSC encoders. The IP core exploits a methodology based on the ABCD matrices model which permits to increase the number of inputs bits processed in parallel. Through an analysis of the proposed network topology and by exploiting data relative to the implementation on Zynq 7000 xc7z010clg400-1 field programmable gate array (FPGA), an estimation of the dependency of the input data rate and of the source occupation on the parallelism degree is performed. Such analysis, together with the BER curves, provides a description of the principal merit parameters of a RSC encoder.

Study on the Application of Multi-Frequency Error Test

2012 ◽  
Vol 433-440 ◽  
pp. 4802-4806
Author(s):  
Xiao Jun He ◽  
Xiao Ping Tian ◽  
Bo Dai
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Field Programmable Gate Array ◽  
Important Application ◽  
Frequency Error ◽  
Telephone Line ◽  
Field Programmable ◽  
Rate Test ◽  
Gate Array ◽  
Micro Controller Unit

In order to test the characteristics of the telephone line, BER (Bit Error Rate) test is one of the most important aspects. The multi-frequency BER test is achieved using FPGA (Field Programmable Gate Array), MCU (Micro Controller Unit) and Modem chip. This design is able to exactly test the telephone line’s bit error whose frequency is between 1.2KHz and 160KHz. repeatedly experiments results show that this method is stable and reliable, and has important application values.

scholarly journals A Streaming High-Throughput Linear Sorter System with Contention Buffering

2011 ◽  
Vol 2011 ◽  
pp. 1-12 ◽  
Author(s):  
Jorge Ortiz ◽  
David Andrews
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
Clock Cycle ◽  
Sorting Networks ◽  
Sorting Algorithms ◽  
Hardware Implementations ◽  
Field Programmable ◽  
Gate Array ◽  
Sorting Efficiency

Popular sorting algorithms do not translate well into hardware implementations. Instead, hardware-based solutions like sorting networks, systolic sorters, and linear sorters exploit parallelism to increase sorting efficiency. Linear sorters, built from identical nodes with simple control, have less area and latency than sorting networks, but they are limited in their throughput. We present a system composed of multiple linear sorters acting in parallel to increase overall throughput. Interleaving is used to increase bandwidth and allow sorting of multiple values per clock cycle, and the amount of interleaving and depth of the linear sorters can be adapted to suit specific applications. Contention for available linear sorters in the system is solved through the use of buffers that accumulate conflicting requests, dispatching them in bulk to reduce latency penalties. Implementation of this system into a field programmable gate array (FPGA) results in a speedup of 68 compared to a MicroBlaze processor running quicksort.

High Speed FPGA Based 128-bit Advance Encryption Standard (AES)

2021 ◽  
Vol 11 ◽  
Author(s):  
Ibrahem M. T. Hamidi ◽  
Farah S. H. Al-aassi
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Design Tool ◽  
Advanced Encryption Standard ◽  
Clock Frequency ◽  
Advance Encryption Standard ◽  
Field Programmable ◽  
Internal Component ◽  
Gate Array

Aim: Achieve high throughput 128 bits FPGA based Advanced Encryption Standard. Background: Field Programmable Gate Array (FPGA) provides an efficient platform for design AES cryptography system. It provides the capability to control over each bit using HDL programming language such as VHDL and Verilog which results an output speed in Gbps rang. Objective: Use Field Programmable Gate Array (FPGA) to design high throughput 128 bits FPGA based Advanced Encryption Standard. Method: Pipelining technique has used to achieve maximum possible speed. The level of pipelining includes round pipelining and internal component pipelining where number of registers inserted in particular places to increase the output speed. The proposed design uses combinatorial logic to implement the byte substitution. The s-box implemented using composed field arithmetic with 7 stages of pipelining to reduce the combinatorial logic level. The presented model has implemented using VHDL in Xilinix ISETM 14.4 design tool. Result: The achieved results were 18.55 Gbps at a clock frequency of 144.96 MHz and area of 1568 Slices in Spartan3 xc3s1000 hardware. Conclusion: The results show that the proposed design reaches a high throughput with acceptable area usage compare with other designs in the literature.

scholarly journals Fuzzy Based Adaptive Controller for on - Chip Communication

2018 ◽  
Vol 7 (3.27) ◽  
pp. 362
Author(s):  
M Jasmin ◽  
T Vigneswaran
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Error Detection ◽  
Input Data ◽  
Fuzzy Controller ◽  
Proper Time ◽  
System On Chip ◽  
Coding Scheme ◽  
Error Detection And Correction ◽  
On Chip

Occurrence of bit error is more when communication takes place in System on chip environment. By employing proper error detection and correction codes the bit error rate can be considerably reduced in On-chip communication. As System on chip involves heterogeneous system the efficiency of communication is improved when reconfigurable multiple coding schemes are preferred. Depending upon the requirements for various subsystem the correct code has to be selected. Due to the variations in input demands based on various subsystems the proper selection of codes become fuzzy in nature. In this paper Fuzzy Controller is designed to select the correct coding scheme. Inputs are given to the fuzzy controller based on the application demand of the user. The input parameters are minimum bit error rate, computational complexity and correlation level of the input data. Fuzzy Controller employs three membership functions and 27 rules to select the appropriate coding scheme. The selected coding scheme should be communicated at the proper time to the decoder. To enable the decoding process selected coding scheme is communicated effectively by using less overhead frame format. To verify the functionality of fuzzy controller random input data sets are used for testing.  

Convolutional Encoders to Minimize Bit-Error-Rate

2000 ◽  
Vol 11 (3) ◽  
pp. 263-269 ◽  
Author(s):  
Amos Lapidoth ◽  
Peter J. Sallaway
Keyword(s):  
Bit Error Rate ◽  
Error Rate ◽  
Convolutional Encoders

scholarly journals METHODS OF MODELING WIRELESS SENSOR NETWORKS TOPOLOGY CONSIDERING INTERNODAL INTERFERENCE

2020 ◽  
Vol 2020 (3) ◽  
pp. 34-44
Author(s):  
Vladimir Vasilevich Fedorenko ◽  
Vladimir Valerevich Samoylenko ◽  
Daria Vladimirovna Alduschenko ◽  
Igor Vladimirovich Emelyanenko
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Network Topology ◽  
Bit Error Rate ◽  
Error Rate ◽  
Frequency Separation ◽  
Wireless Sensor ◽  
Reliability Indicator ◽  
Useful Signal ◽  
The Impact

The article presents the analysis of developing methods of wireless sensor networks (WSNs) topologies based on a graph structure. It indicates the prevalence of tolerance criteria for de-scribing the links between nodes, for example, the limiting distance of radio communication, a sufficient ratio of signal/energy (interference + noise). To consider the impact of inter-node interference on the network topology it is proposed to use the permissible values of bit error probabilities or erasing an information packet in case of distortion of at least one its elements as a criterion for stable communication. The algorithm for calculating an analytical model of internode communication channel is presented to evaluate the effect of intra-network additive and multiplicative noise on the reliability indicator of incoherent message reception in the form of a bit error rate. Expression for the coefficient of structural interaction of the received signal and the interference complex is obtained, which allows considering the dependence of bit error rate on the energy components of individual interference at the receiver input, frequency separation value of a signal and values of each disturbance, their phase shifts and the duration of the information bit. There has been considered practical application of the WSNs topology modeling technique for the internode communication channels with Rice fading of a useful signal and Rayleigh fading of an intra-network interference complex (a case study of using CC2500 modems as part of WSNs nodes). As a result of analysis, there have been determined the relations between nodes, for which the bit error rates do not exceed the allowable value established by requirements for channel capacity and the length of information packets. The presented modeling approach proves the possibility of improving the network topology due to developing the internode links by redistributing the frequency resource between the nodes or adjusting the operation modes of the modems.

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