scholarly journals A New Configuration of Three-Level ZSI Using Transistor Clamped Topology

Energies ◽  
2020 ◽  
Vol 13 (6) ◽  
pp. 1469
Author(s):  
Santosh Sonar

In this paper, a three-level ZSI (impedance source inverter) based on transistor clamped theory is proposed. It uses the least number of switch counts and associated gate circuitry among all existing topologies of three-level ZSI without any performance degradation. The existing three-level ZSI topologies require three power switches to be turned ON for upper-lower shoot-through (ULST), and four power switches to be turned ON for full dc-link shoot-through (FST). However, with the proposed configuration, upper–lower shoot-through (ULST) and full dc-link shoot-through (FST) is inserted by turning ON only two power semiconductors. A comparison between diode clamped, transistor clamped, and t-type is presented. The proposed topology can realize any of the existing sine-triangle- or space vector-based PWM (pulse width modulation) schemes, and all existing configurations of three-level ZSI can merge into the proposed inverter configuration.

2020 ◽  
Vol 13 (6) ◽  
pp. 307-317
Author(s):  
Hoai Nguyen ◽  
◽  
Dinh Nguyen ◽  
Minh Chau ◽  
◽  
...  

In this paper, a novel approach to realize the carrier-based pulse width modulation (CBPWM) method for indirect matrix converter (IMC) is presented. The advantage of the proposed CBPWM method is that only one triangular carrier signal with constant gradient falling and rising edges is used to generate the PWM to the power switches in both the rectifier and the inverter stages of IMC. The analysis of the proposed CBPWM method is based on the space vector approach and the relationship between CBPWM and space vector pulse width modulation (SVPWM) methods is provided. In this paper, four CBPWM methods called: sinusoidal PWM, third harmonic injection PWM, symmetrical PWM and discontinuous PWM are presented. These different CBPWM schemes are established according to the distribution of zero vectors and the switching pattern of the SVPWM method. The comparison of output voltage performance with different CBPWM schemes are investigated. Compared to the conventional method the calculation time of the proposed method is reduced around 50%. Concretely, the calculation time of the SVPWM method is 45 μs, while the calculation time of the proposed method is 22 μs. The experiments have been carried out to show the effectiveness of the proposed method.


2013 ◽  
Vol 7 (2) ◽  
pp. 19-25
Author(s):  
B. Arundhati ◽  
◽  
K. Alice Mary ◽  
Surya Kalavathi M ◽  
K. Shankar ◽  
...  

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