scholarly journals Effects of Interface Trap on Transient Negative Capacitance Effect: Phase Field Model

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2141
Author(s):  
Taegeon Kim ◽  
Changhwan Shin
Keyword(s):  
Phase Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Model ◽  
Phase Field Model ◽  
Ferroelectric Materials ◽  
Interface Trap ◽  
Negative Capacitance ◽  
Effect Transistor ◽  
The Impact

Ferroelectric materials have received significant attention as next-generation materials for gates in transistors because of their negative differential capacitance. Emerging transistors, such as the negative capacitance field effect transistor (NCFET) and ferroelectric field-effect transistor (FeFET), are based on the use of ferroelectric materials. In this work, using a multidomain 3D phase field model (based on the time-dependent Ginzburg–Landau equation), we investigate the impact of the interface-trapped charge (Qit) on the transient negative capacitance in a ferroelectric capacitor (i.e., metal/Zr-HfO2/heavily doped Si) in series with a resistor. The simulation results show that the interface trap reinforces the effect of transient negative capacitance.

scholarly journals The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 582 ◽  
Author(s):  
Raymond Hueting
Keyword(s):  
Lead Zirconate Titanate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ferroelectric Material ◽  
Ferroelectric Materials ◽  
Polarization Field ◽  
Maximum Speed ◽  
Negative Capacitance ◽  
New Device ◽  
Effect Transistor

For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π -FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., “hard” ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π -FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π -FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.

Intrinsic switching in Si-doped HfO2: A study of Curie–Weiss law and its implications for negative capacitance field-effect transistor

2021 ◽  
Vol 118 (19) ◽  
pp. 192904
Author(s):  
Carlotta Gastaldi ◽  
Matteo Cavalieri ◽  
Ali Saeidi ◽  
Eamon O'Connor ◽  
Sadegh Kamaei ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Negative Capacitance ◽  
Si Doped ◽  
Effect Transistor

Effect of Metal - Silicon Nanowire Contacts on the Performance of Accumulation Metal Oxide Semiconductor Field Effect Transistor

2008 ◽  
Vol 1144 ◽  
Author(s):  
Pranav Garg ◽  
Yi Hong ◽  
Md. Mash-Hud Iqbal ◽  
Stephen J. Fonash
Keyword(s):  
Metal Oxide ◽  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Silicon Nanowire ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Effect Transistor ◽  
The Impact

ABSTRACTRecently, we have experimentally demonstrated a very simply structured unipolar accumulation-type metal oxide semiconductor field effect transistor (AMOSFET) using grow-in-place silicon nanowires. The AMOSFET consists of a single doping type nanowire, metal source and drain contacts which are separated by a partially gated region. Despite its simple configuration, it is capable of high performance thereby offering the potential of a low manufacturing-cost transistor. Since the quality of the metal/semiconductor ohmic source and drain contacts impacts AMOSFET performance, we repot here on initial exploration of contact variations and of the impact of thermal process history. With process optimization, current on/off ratios of 106 and subthreshold swings of 70 mV/dec have been achieved with these simple devices

scholarly journals The impact of channel fin width on electrical characteristics of Si-FinFET

2022 ◽  
Vol 12 (1) ◽  
pp. 201
Author(s):  
Yousif Atalla ◽  
Yasir Hashim ◽  
Abdul Nasir Abd. Ghafar
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Environmental Temperature ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Working Temperature ◽  
Effect Transistor ◽  
The Impact ◽  
The Ideal

<span>This paper studies the impact of fin width of channel on temperature and electrical characteristics of fin field-effect transistor (FinFET). The simulation tool multi-gate field effect transistor (MuGFET) has been used to examine the FinFET characteristics. Transfer characteristics with various temperatures and channel fin width (W<sub>F</sub>=5, 10, 20, 40, and 80 nm) are at first simulated in this study. The results show that the increasing of environmental temperature tends to increase threshold voltage, while the subthreshold swing (SS) and drain-induced barrier lowering (DIBL) rise with rising working temperature. Also, the threshold voltage decreases with increasing channel fin width of transistor, while the SS and DIBL increase with increasing channel fin width of transistor, at minimum channel fin width, the SS is very near to the best and ideal then its value grows and going far from the ideal value with increasing channel fin width. So, according to these conditions, the minimum value as possible of fin width is the preferable one for FinFET with better electrical characteristics.</span>

scholarly journals Numerical Evaluation of the Effect of Geometric Tolerances on the High-Frequency Performance of Graphene Field-Effect Transistors

Nanomaterials ◽  
2021 ◽  
Vol 11 (11) ◽  
pp. 3121
Author(s):  
Monica La Mura ◽  
Patrizia Lamberti ◽  
Vincenzo Tucci
Keyword(s):  
High Frequency ◽  
Communication Systems ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Geometrical Parameters ◽  
Effect Transistor ◽  
Rf Performance ◽  
The Impact

The interest in graphene-based electronics is due to graphene’s great carrier mobility, atomic thickness, resistance to radiation, and tolerance to extreme temperatures. These characteristics enable the development of extremely miniaturized high-performing electronic devices for next-generation radiofrequency (RF) communication systems. The main building block of graphene-based electronics is the graphene-field effect transistor (GFET). An important issue hindering the diffusion of GFET-based circuits on a commercial level is the repeatability of the fabrication process, which affects the uncertainty of both the device geometry and the graphene quality. Concerning the GFET geometrical parameters, it is well known that the channel length is the main factor that determines the high-frequency limitations of a field-effect transistor, and is therefore the parameter that should be better controlled during the fabrication. Nevertheless, other parameters are affected by a fabrication-related tolerance; to understand to which extent an increase of the accuracy of the GFET layout patterning process steps can improve the performance uniformity, their impact on the GFET performance variability should be considered and compared to that of the channel length. In this work, we assess the impact of the fabrication-related tolerances of GFET-base amplifier geometrical parameters on the RF performance, in terms of the amplifier transit frequency and maximum oscillation frequency, by using a design-of-experiments approach.

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