SW-VHDL Co-Verification Environment Using Open Source Tools
The verification of complex digital designs often involves the use of expensive simulators. The present paper proposes an approach to verify a specific family of complex hardware/software systems, whose hardware part, running on an FPGA, communicates with a software counterpart executed on an external processor, such as a user/operator software running on an external PC. The hardware is described in VHDL and the software may be described in any computer language that can be interpreted or compiled into a (Linux) executable file. The presented approach uses open source tools, avoiding expensive license costs and usage restrictions.
2020 ◽
Vol 30
(09)
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pp. 1263-1288
2007 ◽
Vol 32
(6)
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pp. 7
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2015 ◽
Vol 5
(4)
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pp. 24-35
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