scholarly journals Multiprotocol Authentication Device for HPC and Cloud Environments Based on Elliptic Curve Cryptography

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1148
Author(s):  
Antonio F. Díaz ◽  
Ilia Blokhin ◽  
Mancia Anguita ◽  
Julio Ortega ◽  
Juan J. Escobar
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
High Performance ◽  
Low Cost ◽  
System On Chip ◽  
Access To Services ◽  
Multifactor Authentication ◽  
Server Systems ◽  
On Chip ◽  
The Impact

Multifactor authentication is a relevant tool in securing IT infrastructures combining two or more credentials. We can find smartcards and hardware tokens to leverage the authentication process, but they have some limitations. Users connect these devices in the client node to log in or request access to services. Alternatively, if an application wants to use these resources, the code has to be amended with bespoke solutions to provide access. Thanks to advances in system-on-chip devices, we can integrate cryptographically robust, low-cost solutions. In this work, we present an autonomous device that allows multifactor authentication in client–server systems in a transparent way, which facilitates its integration in High-Performance Computing (HPC) and cloud systems, through a generic gateway. The proposed electronic token (eToken), based on the system-on-chip ESP32, provides an extra layer of security based on elliptic curve cryptography. Secure communications between elements use Message Queuing Telemetry Transport (MQTT) to facilitate their interconnection. We have evaluated different types of possible attacks and the impact on communications. The proposed system offers an efficient solution to increase security in access to services and systems.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

2020 ◽  
Vol 17 (4) ◽  
pp. 1852-1856
Author(s):  
P. Bhuvaneshwari ◽  
T. R. Jaya Chandra Lekha
Keyword(s):  
Low Power ◽  
High Performance ◽  
Performance Monitoring ◽  
Low Cost ◽  
System On Chip ◽  
Consumer Electronics ◽  
Compression Scheme ◽  
Control Signals ◽  
And Performance ◽  
On Chip

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.

Wireless CNC Motion Controller Designed with PSoC

2014 ◽  
Vol 898 ◽  
pp. 944-951 ◽  
Author(s):  
Chi Zhang ◽  
Zhao Hui Ye ◽  
Yong Ming Zhou
Keyword(s):  
High Performance ◽  
System On Chip ◽  
Numerical Control ◽  
Motion Controller ◽  
Joint Axis ◽  
Chip Technology ◽  
On Chip ◽  
Cnc Controller ◽  
The Impact ◽  
Circular Interpolation

Numerical control (NC) technology is a kind of technology combined with electronics, machinery manufacturing, and other interdisciplinary combination of technologies. It is an important part of modern manufacturing. Currently, NC technology is developing towards the open CNC system with extensibility and interchangeability, while the modern electronic technology is developing towards the programmable technology and SoC (System-on-Chip) technology. However, current CNC controller designed with SoC is still in the research stage and not practical yet. In this paper, a practical CNC motion controller is built with modern PSoC (Programmable System-on-Chip) with wireless Ethernet interface. This controller has a high-performance microprocessor, numbers of free configurable analog and digital devices and IO (input/output) interfaces, and many kinds of communication interfaces. Therefore, it has good real-time control functions and communication functions. Experiments for controlling a three joint-axis engraving machine show that the controller can achieve high performance of parallel control of the three joint-axis linear interpolation and two joint-axis circular interpolation, and high performance of the trapezoidal and S-shape speed control. In addition, in order to reduce the impact to the motor and increase the system efficiency, a kind of look-ahead algorithm for velocity control with low time cost is used.

scholarly journals An Efficient Cache Organization for On-Chip Multiprocessor Networks

2015 ◽  
Vol 5 (3) ◽  
pp. 503
Author(s):  
Medhat Awadalla ◽  
Ahmed M. Sadek
Keyword(s):  
High Performance ◽  
Cache Coherence ◽  
Low Cost ◽  
System On Chip ◽  
Cache Memory ◽  
Processing Unit ◽  
Single Chip ◽  
Chip Area ◽  
Shared Cache ◽  
On Chip

To meet the growing computation-intensive applications and the needs of low-power, high-performance systems, the number of computing resources in single-chip has enormously increased. By adding many computing resources to build a system in System-on-Chip, its interconnection between each other becomes another challenging issue. In most System-on-Chip applications, a shared bus interconnection which needs an arbitration logic to serialize several bus access requests, is adopted to communicate with each integrated processing unit because of its low-cost and simple control characteristics. This paper focuses on the interconnection design issues of area, power and performance of chip multi-processors with shared cache memory. It shows that having shared cache memory contributes to the performance improvement, however, typical interconnection between cores and the shared cache using crossbar occupies most of the chip area, consumes a lot of power and does not scale efficiently with increased number of cores. New interconnection mechanisms are needed to address these issues. This paper proposes an architectural paradigm in an attempt to gain the advantages of having shared cache with the avoidance of penalty imposed by the crossbar interconnect. The proposed architecture achieves smaller area occupation allowing more space to add additional cache memory. It also reduces power consumption compared to the existing crossbar architecture. Furthermore, the paper presents a modified cache coherence algorithm called Tuned-MESI. It is based on the typical MESI cache coherence algorithm however it is tuned and tailored for the suggested architecture. The achieved results of the conducted simulated experiments show that the developed architecture produces less broadcast operations compared to the typical algorithm.

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

2021 ◽  
pp. 1-12
Author(s):  
Arun Prasath Raveendran ◽  
Jafar A. Alzubi ◽  
Ramesh Sekaran ◽  
Manikandan Ramachandran
Keyword(s):  
High Performance ◽  
Standard Technique ◽  
System On Chip ◽  
Mixed Integer ◽  
Multiprocessor System ◽  
Compound System ◽  
Available Bandwidth ◽  
Mip Model ◽  
Fpga Chip ◽  
On Chip

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

scholarly journals Engineered tunneling layer with enhanced impact ionization for detection improvement in graphene/silicon heterojunction photodetectors

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Jun Yin ◽  
Lian Liu ◽  
Yashu Zang ◽  
Anni Ying ◽  
Wenjie Hui ◽  
...  
Keyword(s):  
High Performance ◽  
Impact Ionization ◽  
Low Cost ◽  
Atomic Layer ◽  
Light Illumination ◽  
Insulation Material ◽  
Defect States ◽  
Uv Illumination ◽  
Layer Deposition ◽  
The Impact

AbstractHere, an engineered tunneling layer enhanced photocurrent multiplication through the impact ionization effect was proposed and experimentally demonstrated on the graphene/silicon heterojunction photodetectors. With considering the suitable band structure of the insulation material and their special defect states, an atomic layer deposition (ALD) prepared wide-bandgap insulating (WBI) layer of AlN was introduced into the interface of graphene/silicon heterojunction. The promoted tunneling process from this designed structure demonstrated that can effectively help the impact ionization with photogain not only for the regular minority carriers from silicon, but also for the novel hot carries from graphene. As a result, significantly enhanced photocurrent as well as simultaneously decreased dark current about one order were accomplished in this graphene/insulation/silicon (GIS) heterojunction devices with the optimized AlN thickness of ~15 nm compared to the conventional graphene/silicon (GS) devices. Specifically, at the reverse bias of −10 V, a 3.96-A W−1 responsivity with the photogain of ~5.8 for the peak response under 850-nm light illumination, and a 1.03-A W−1 responsivity with ∼3.5 photogain under the 365 nm ultraviolet (UV) illumination were realized, which are even remarkably higher than those in GIS devices with either Al2O3 or the commonly employed SiO2 insulation layers. This work demonstrates a universal strategy to fabricate broadband, low-cost and high-performance photo-detecting devices towards the graphene-silicon optoelectronic integration.

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