scholarly journals Fault Diagnosis of Open-Switch Failure in a Grid-Connected Three-Level Si/SiC Hybrid ANPC Inverter

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 399 ◽  
Author(s):  
Bong Hyun Kwon ◽  
Sang-Hun Kim ◽  
Seok-Min Kim ◽  
Kyo-Beum Lee
Keyword(s):  
Diagnostic Method ◽  
Field Effect Transistors ◽  
Open Circuit ◽  
Bipolar Transistors ◽  
Neutral Point ◽  
Oxide Semiconductor ◽  
Short Period ◽  
Open Switch ◽  
Stationary Reference Frame ◽  
The Individual

A diagnostic method for an open-circuit switch failure in a hybrid active neutral-point clamped (HANPC) inverter is proposed in this paper. The switching leg of the HANPC inverter consists of four silicon insulated gate bipolar transistors and two silicon carbide metal-oxide-semiconductor field-effect transistors to achieve higher efficiency and power density compared to conventional neutral-point clamped inverters. When an open-circuit failure occurs in a switching device, the output current is severely distorted, causing damage to the inverter and the connected loads. The proposed diagnostic method aims to detect the open-switch failure and protect the related devices without additional sensors or circuits. The faulty conditions of six different switches are investigated based on the current distortion in the stationary reference frame. By analyzing the individual characteristic of each switch failure, it is possible to detect the exact location of the failed switch in a short period. The effectiveness and feasibility of the proposed fault-diagnostic method are verified using simulation and experimental results.

scholarly journals Extended T-type Inverter

2018 ◽  
Vol 3 (1) ◽  
pp. 55-64
Author(s):  
Jacek Rąbkowski ◽  
Rafał Kopacz
Keyword(s):  
Low Voltage ◽  
Field Effect Transistors ◽  
Schottky Diodes ◽  
Input Voltage ◽  
Neutral Point ◽  
Oxide Semiconductor ◽  
Laboratory Model ◽  
Power Losses ◽  
Power Semiconductor ◽  
Point Potential

Abstract This paper presents a new concept for a power electronic converter - the extended T-type (eT) inverter, which is a combination of a three-phase inverter and a three-level direct current (dc)/dc converter. The novel converter shows better performance than a comparable system composed of two converters: a T-type inverter and a boost converter. At first, the three-level dc/dc converter is able to boost the input voltage but also affects the neutral point potential. The operation principles of the eT inverter are explained and a simulation study of the SiC-based 6 kVA system is presented in this paper. Presented results show a serious reduction of the DC-link capacitors and the input inductor. Furthermore, suitable SiC power semiconductor devices are selected and power losses are estimated using Saber software in reference to a comparative T-type inverter. According to the simulations, the 50 kHz/6 kVA inverter feed from the low voltage (250 V) shows <2.5% of power losses in the suggested SiC metal oxide-semiconductor field-effect transistors (MOSFETs) and Schottky diodes. Finally, a 6 kVA laboratory model was designed, built and tested. Conducted measurements show that despite low capacitance (2 × 30 μF/450 V), the neutral point potential is balanced, and the observed efficiency of the inverter is around 96%.

scholarly journals Switch Open-Fault Detection for a Three-Phase Hybrid Active Neutral-Point-Clamped Rectifier

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1437
Author(s):  
Sang-Hun Kim ◽  
Seok-Min Kim ◽  
Sungmin Park ◽  
Kyo-Beum Lee
Keyword(s):  
Fault Detection ◽  
Reactive Power ◽  
Detection Method ◽  
Field Effect Transistors ◽  
Individual Characteristics ◽  
Neutral Point ◽  
Phase Current ◽  
Three Phase ◽  
Open Switch ◽  
Open Faults

This paper proposes a fault-detection method for open-switch failures in hybrid active neutral-point-clamped (HANPC) rectifiers. The basic HANPC topology comprises two SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) and four Si insulated-gate bipolar transistors (IGBTs). A three-phase rectifier system using the HANPC topology can produce higher efficiency and lower current harmonics. An open-switch fault in a HANPC rectifier can be a MOSFET or IGBT fault. In this work, faulty cases of six different switches are analyzed based on the current distortion in the stationary reference frame. Open faults in MOSFET switches cause immediate and remarkable current distortions, whereas, open faults in IGBT switches are difficult to detect using conventional methods. To detect an IGBT fault, the proposed detection method utilizes some of the reactive power in a certain period to make an important difference, using the direct-quadrant (dq)-axis current information derived from the three-phase current. Thus, the proposed detection method is based on three-phase current measurements and does not use additional hardware. By analyzing the individual characteristics of each switch failure, the failed switch can be located exactly. The effectiveness and feasibility of the proposed fault-detection method are verified through PSIM simulations and experimental results.

scholarly journals Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1759
Author(s):  
Akinobu Teramoto
Keyword(s):  
Field Effect Transistors ◽  
Low Frequency ◽  
Evaluation Methods ◽  
Oxide Semiconductor ◽  
Frequency Noise ◽  
Low Frequency Noise ◽  
Semiconductor Memory ◽  
Telegraph Noise ◽  
Short Period ◽  
Current Flows

Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO2/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented.

TEM evaluation of graded SixGe1-x heterolayers

1991 ◽  
Vol 49 ◽  
pp. 894-895
Author(s):  
N. David Theodore ◽  
Mamoru Tomozane ◽  
Ming Liaw
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Gas Flow ◽  
Field Effect Transistors ◽  
Chemical Vapor ◽  
Dark Field ◽  
Bipolar Transistors ◽  
Structural Quality ◽  
Weak Beam ◽  
Transmission Electron ◽  
And Behavior

There is extensive interest in SiGe for use in heterojunction bipolar transistors. SiGe/Si superlattices are also of interest because of their potential for use in infrared detectors and field-effect transistors. The processing required for these materials is quite compatible with existing silicon technology. However, before SiGe can be used extensively for devices, there is a need to understand and then control the origin and behavior of defects in the materials. The present study was aimed at investigating the structural quality of, and the behavior of defects in, graded SiGe layers grown by chemical vapor deposition (CVD).The structures investigated in this study consisted of Si1-xGex[x=0.16]/Si1-xGex[x= 0.14, 0.13, 0.12, 0.10, 0.09, 0.07, 0.05, 0.04, 0.005, 0]/epi-Si/substrate heterolayers grown by CVD. The Si1-xGex layers were isochronally grown [t = 0.4 minutes per layer], with gas-flow rates being adjusted to control composition. Cross-section TEM specimens were prepared in the 110 geometry. These were then analyzed using two-beam bright-field, dark-field and weak-beam images. A JEOL JEM 200CX transmission electron microscope was used, operating at 200 kV.

TEM study of Cosi2 formation via annealing of Co-Ti bilayers on Si

1995 ◽  
Vol 53 ◽  
pp. 464-465
Author(s):  
N. David Theodore ◽  
Andre Vantomme ◽  
Peter Crazier
Keyword(s):  
Thermal Instability ◽  
Lattice Mismatch ◽  
Field Effect Transistors ◽  
Contact Layer ◽  
Interface Roughness ◽  
Oxide Semiconductor ◽  
Surface Layers ◽  
Silicide Layer ◽  
Small Lattice ◽  
Buried Layers

Contact is typically made to source/drain regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) by use of TiSi2 or CoSi2 layers followed by AI(Cu) metal lines. A silicide layer is used to reduce contact resistance. TiSi2 or CoSi2 are chosen for the contact layer because these silicides have low resistivities (~12-15 μΩ-cm for TiSi2 in the C54 phase, and ~10-15 μΩ-cm for CoSi2). CoSi2 has other desirable properties, such as being thermally stable up to >1000°C for surface layers and >1100°C for buried layers, and having a small lattice mismatch with silicon, -1.2% at room temperature. During CoSi2 growth, Co is the diffusing species. Electrode shorts and voids which can arise if Si is the diffusing species are therefore avoided. However, problems can arise due to silicide-Si interface roughness (leading to nonuniformity in film resistance) and thermal instability of the resistance upon further high temperature annealing. These problems can be avoided if the CoSi2 can be grown epitaxially on silicon.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

scholarly journals Evaluation of VTH and RON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 441
Author(s):  
Marcello Cioni ◽  
Alessandro Bertacchini ◽  
Alessandro Mucci ◽  
Nicolò Zagni ◽  
Giovanni Verzellesi ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Driving Voltage ◽  
Drain Voltage ◽  
Current Increase ◽  
Mode Operation ◽  
Switch Mode ◽  
Gate Signal ◽  
A Current ◽  
Parameter Monitoring

In this paper, we investigate the evolution of threshold voltage (VTH) and on-resistance (RON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative VTH shifts (i.e., VTH decrease) and negative RON drifts (i.e., RON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (VGH) and (ii) off-state drain voltage (VPH). We found that VTH reduction leads to a current increase, thus yielding RON to decrease. This correlation was explained by the RON dependence on the overdrive voltage (VGS–VTH). We also found that gate-related effects dominate the parameter drifts at low VPH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high VPH are completely recoverable within 1000 s from the VPH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed VTH and RON drifts.

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